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x86emul: support AVX512{F,BW,DQ} extract insns
Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
This commit is contained in:
Jan Beulich committed
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2 files changed
+83
-6
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@@ -212,6 +212,7 @@ static const struct test avx512f_all[] = {
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};
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static const struct test avx512f_128[] = {
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INSN(extractps, 66, 0f3a, 17, el, d, el),
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INSN(mov, 66, 0f, 6e, el, dq64, el),
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INSN(mov, 66, 0f, 7e, el, dq64, el),
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INSN(movq, f3, 0f, 7e, el, q, el),
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@@ -221,10 +222,14 @@ static const struct test avx512f_128[] = {
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static const struct test avx512f_no128[] = {
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INSN(broadcastf32x4, 66, 0f38, 1a, el_4, d, vl),
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INSN(broadcastsd, 66, 0f38, 19, el, q, el),
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INSN(extractf32x4, 66, 0f3a, 19, el_4, d, vl),
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INSN(extracti32x4, 66, 0f3a, 39, el_4, d, vl),
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};
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static const struct test avx512f_512[] = {
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INSN(broadcastf64x4, 66, 0f38, 1b, el_4, q, vl),
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INSN(extractf64x4, 66, 0f3a, 1b, el_4, q, vl),
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INSN(extracti64x4, 66, 0f3a, 3b, el_4, q, vl),
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};
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static const struct test avx512bw_all[] = {
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@@ -280,6 +285,12 @@ static const struct test avx512bw_all[] = {
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INSN(ptestnm, f3, 0f38, 26, vl, bw, vl),
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};
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static const struct test avx512bw_128[] = {
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INSN(pextrb, 66, 0f3a, 14, el, b, el),
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// pextrw, 66, 0f, c5, w
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INSN(pextrw, 66, 0f3a, 15, el, w, el),
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};
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static const struct test avx512dq_all[] = {
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INSN_PFP(and, 0f, 54),
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INSN_PFP(andn, 0f, 55),
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@@ -288,13 +299,21 @@ static const struct test avx512dq_all[] = {
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INSN_PFP(xor, 0f, 57),
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};
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static const struct test avx512dq_128[] = {
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INSN(pextr, 66, 0f3a, 16, el, dq64, el),
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};
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static const struct test avx512dq_no128[] = {
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INSN(broadcastf32x2, 66, 0f38, 19, el_2, d, vl),
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INSN(broadcastf64x2, 66, 0f38, 1a, el_2, q, vl),
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INSN(extractf64x2, 66, 0f3a, 19, el_2, q, vl),
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INSN(extracti64x2, 66, 0f3a, 39, el_2, q, vl),
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};
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static const struct test avx512dq_512[] = {
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INSN(broadcastf32x8, 66, 0f38, 1b, el_8, d, vl),
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INSN(extractf32x8, 66, 0f3a, 1b, el_8, d, vl),
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INSN(extracti32x8, 66, 0f3a, 3b, el_8, d, vl),
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};
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static const unsigned char vl_all[] = { VL_512, VL_128, VL_256 };
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@@ -632,7 +651,9 @@ void evex_disp8_test(void *instr, struct x86_emulate_ctxt *ctxt,
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RUN(avx512f, no128);
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RUN(avx512f, 512);
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RUN(avx512bw, all);
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RUN(avx512bw, 128);
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RUN(avx512dq, all);
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RUN(avx512dq, 128);
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RUN(avx512dq, no128);
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RUN(avx512dq, 512);
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}
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@@ -512,9 +512,13 @@ static const struct ext0f3a_table {
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[0x0a ... 0x0b] = { .simd_size = simd_scalar_opc },
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[0x0c ... 0x0d] = { .simd_size = simd_packed_fp },
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[0x0e ... 0x0f] = { .simd_size = simd_packed_int },
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[0x14 ... 0x17] = { .simd_size = simd_none, .to_mem = 1, .two_op = 1 },
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[0x14] = { .simd_size = simd_none, .to_mem = 1, .two_op = 1, .d8s = 0 },
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[0x15] = { .simd_size = simd_none, .to_mem = 1, .two_op = 1, .d8s = 1 },
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[0x16] = { .simd_size = simd_none, .to_mem = 1, .two_op = 1, .d8s = d8s_dq64 },
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[0x17] = { .simd_size = simd_none, .to_mem = 1, .two_op = 1, .d8s = 2 },
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[0x18] = { .simd_size = simd_128 },
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[0x19] = { .simd_size = simd_128, .to_mem = 1, .two_op = 1 },
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[0x19] = { .simd_size = simd_128, .to_mem = 1, .two_op = 1, .d8s = 4 },
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[0x1b] = { .simd_size = simd_256, .to_mem = 1, .two_op = 1, .d8s = d8s_vl_by_2 },
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[0x1d] = { .simd_size = simd_other, .to_mem = 1, .two_op = 1 },
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[0x1e ... 0x1f] = { .simd_size = simd_packed_int, .d8s = d8s_vl },
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[0x20] = { .simd_size = simd_none },
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@@ -523,7 +527,8 @@ static const struct ext0f3a_table {
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[0x25] = { .simd_size = simd_packed_int, .d8s = d8s_vl },
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[0x30 ... 0x33] = { .simd_size = simd_other, .two_op = 1 },
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[0x38] = { .simd_size = simd_128 },
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[0x39] = { .simd_size = simd_128, .to_mem = 1, .two_op = 1 },
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[0x39] = { .simd_size = simd_128, .to_mem = 1, .two_op = 1, .d8s = 4 },
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[0x3b] = { .simd_size = simd_256, .to_mem = 1, .two_op = 1, .d8s = d8s_vl_by_2 },
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[0x3e ... 0x3f] = { .simd_size = simd_packed_int, .d8s = d8s_vl },
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[0x40 ... 0x41] = { .simd_size = simd_packed_fp },
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[0x42] = { .simd_size = simd_packed_int },
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@@ -2676,6 +2681,8 @@ x86_decode_0f3a(
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... X86EMUL_OPC_66(0, 0x17): /* pextr*, extractps */
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case X86EMUL_OPC_VEX_66(0, 0x14)
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... X86EMUL_OPC_VEX_66(0, 0x17): /* vpextr*, vextractps */
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case X86EMUL_OPC_EVEX_66(0, 0x14)
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... X86EMUL_OPC_EVEX_66(0, 0x17): /* vpextr*, vextractps */
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case X86EMUL_OPC_VEX_F2(0, 0xf0): /* rorx */
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break;
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@@ -8881,9 +8888,9 @@ x86_emulate(
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opc[0] = b;
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/* Convert memory/GPR operand to (%rAX). */
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rex_prefix &= ~REX_B;
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vex.b = 1;
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evex.b = vex.b = 1;
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if ( !mode_64bit() )
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vex.w = 0;
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evex.w = vex.w = 0;
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opc[1] = modrm & 0x38;
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opc[2] = imm1;
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opc[3] = 0xc3;
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@@ -8893,7 +8900,10 @@ x86_emulate(
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--opc;
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}
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copy_REX_VEX(opc, rex_prefix, vex);
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if ( evex_encoded() )
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copy_EVEX(opc, evex);
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else
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copy_REX_VEX(opc, rex_prefix, vex);
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invoke_stub("", "", "=m" (dst.val) : "a" (&dst.val));
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put_stub(stub);
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@@ -8918,6 +8928,52 @@ x86_emulate(
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opc = init_prefixes(stub);
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goto pextr;
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case X86EMUL_OPC_EVEX_66(0x0f, 0xc5): /* vpextrw $imm8,xmm,reg */
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generate_exception_if(ea.type != OP_REG, EXC_UD);
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/* Convert to alternative encoding: We want to use a memory operand. */
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evex.opcx = ext_0f3a;
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b = 0x15;
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modrm <<= 3;
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evex.r = evex.b;
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evex.R = evex.x;
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/* fall through */
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case X86EMUL_OPC_EVEX_66(0x0f3a, 0x14): /* vpextrb $imm8,xmm,r/m */
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case X86EMUL_OPC_EVEX_66(0x0f3a, 0x15): /* vpextrw $imm8,xmm,r/m */
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case X86EMUL_OPC_EVEX_66(0x0f3a, 0x16): /* vpextr{d,q} $imm8,xmm,r/m */
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case X86EMUL_OPC_EVEX_66(0x0f3a, 0x17): /* vextractps $imm8,xmm,r/m */
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generate_exception_if((evex.lr || evex.reg != 0xf || !evex.RX ||
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evex.opmsk || evex.brs),
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EXC_UD);
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if ( !(b & 2) )
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host_and_vcpu_must_have(avx512bw);
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else if ( !(b & 1) )
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host_and_vcpu_must_have(avx512dq);
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else
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host_and_vcpu_must_have(avx512f);
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get_fpu(X86EMUL_FPU_zmm);
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opc = init_evex(stub);
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goto pextr;
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case X86EMUL_OPC_EVEX_66(0x0f3a, 0x19): /* vextractf32x4 $imm8,{y,z}mm,xmm/m128{k} */
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/* vextractf64x2 $imm8,{y,z}mm,xmm/m128{k} */
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case X86EMUL_OPC_EVEX_66(0x0f3a, 0x39): /* vextracti32x4 $imm8,{y,z}mm,xmm/m128{k} */
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/* vextracti64x2 $imm8,{y,z}mm,xmm/m128{k} */
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if ( evex.w )
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host_and_vcpu_must_have(avx512dq);
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generate_exception_if(!evex.lr || evex.brs, EXC_UD);
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fault_suppression = false;
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goto avx512f_imm8_no_sae;
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case X86EMUL_OPC_EVEX_66(0x0f3a, 0x1b): /* vextractf32x8 $imm8,zmm,ymm/m256{k} */
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/* vextractf64x4 $imm8,zmm,ymm/m256{k} */
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case X86EMUL_OPC_EVEX_66(0x0f3a, 0x3b): /* vextracti32x8 $imm8,zmm,ymm/m256{k} */
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/* vextracti64x4 $imm8,zmm,ymm/m256{k} */
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if ( !evex.w )
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host_and_vcpu_must_have(avx512dq);
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generate_exception_if(evex.lr != 2 || evex.brs, EXC_UD);
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fault_suppression = false;
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goto avx512f_imm8_no_sae;
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case X86EMUL_OPC_VEX_66(0x0f3a, 0x1d): /* vcvtps2ph $imm8,{x,y}mm,xmm/mem */
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{
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uint32_t mxcsr;
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