From 014f835efaf9caa9a112b7f7a7ffad6dd682c77d Mon Sep 17 00:00:00 2001 From: Jan Beulich Date: Wed, 7 Aug 2013 16:55:05 +0200 Subject: [PATCH] x86: refine FPU selector handling code for XSAVEOPT Some extra tweaks are necessary to deal with the situation of XSAVEOPT not writing the FPU portion of the save image (due to it detecting that the register state did not get modified since the last XRSTOR). Signed-off-by: Jan Beulich Tested-by: Ben Guthro Acked-by: Keir Fraser master commit: c58d9f2f4844c2ce8859a8d0f26a54cd058eb51f master date: 2013-08-05 18:42:37 +0200 --- xen/arch/x86/xstate.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/xen/arch/x86/xstate.c b/xen/arch/x86/xstate.c index d52dbd715c..ce94d282f2 100644 --- a/xen/arch/x86/xstate.c +++ b/xen/arch/x86/xstate.c @@ -71,10 +71,28 @@ void xsave(struct vcpu *v, uint64_t mask) if ( word_size <= 0 || !is_pv_32bit_vcpu(v) ) { + typeof(ptr->fpu_sse.fip.sel) fcs = ptr->fpu_sse.fip.sel; + typeof(ptr->fpu_sse.fdp.sel) fds = ptr->fpu_sse.fdp.sel; + if ( cpu_has_xsaveopt ) + { + /* + * xsaveopt may not write the FPU portion even when the respective + * mask bit is set. For the check further down to work we hence + * need to put the save image back into the state that it was in + * right after the previous xsaveopt. + */ + if ( word_size > 0 && + (ptr->fpu_sse.x[FPU_WORD_SIZE_OFFSET] == 4 || + ptr->fpu_sse.x[FPU_WORD_SIZE_OFFSET] == 2) ) + { + ptr->fpu_sse.fip.sel = 0; + ptr->fpu_sse.fdp.sel = 0; + } asm volatile ( ".byte 0x48,0x0f,0xae,0x37" : "=m" (*ptr) : "a" (lmask), "d" (hmask), "D" (ptr) ); + } else asm volatile ( ".byte 0x48,0x0f,0xae,0x27" : "=m" (*ptr) @@ -87,7 +105,14 @@ void xsave(struct vcpu *v, uint64_t mask) */ (!(ptr->fpu_sse.fsw & 0x0080) && boot_cpu_data.x86_vendor == X86_VENDOR_AMD) ) + { + if ( cpu_has_xsaveopt && word_size > 0 ) + { + ptr->fpu_sse.fip.sel = fcs; + ptr->fpu_sse.fdp.sel = fds; + } return; + } if ( word_size > 0 && !((ptr->fpu_sse.fip.addr | ptr->fpu_sse.fdp.addr) >> 32) )