From 0f1ca0a3bc8d360b8ecd0231097a2e4d472838db Mon Sep 17 00:00:00 2001 From: Oleksii Kurochko Date: Wed, 3 Jun 2026 08:16:28 +0200 Subject: [PATCH] xen/riscv: fix switch_stack_and_jump() for range beyond 1M MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The `j` instruction (JAL x0) used in switch_stack_and_jump() is a J-type instruction with only a ±1MB range, and that this can be exceeded in some configurations, causing a linker error: relocation truncated to fit: R_RISCV_JAL against `' Replace `j` with `jr` (JALR x0) via an explicit register, which has unlimited range. Found in a downstream branch when UBSAN instrumentation was enabled. Note that the `tail` instruction looks more natural here, but `jr` is chosen instead to avoid depending on how the assembler expands `tail` and which scratch register it uses (`t1` in GAS), which would need to be listed in the clobber section of `asm volatile`. Fixes: e66003e7be199 ("xen/riscv: introduce setup_initial_pages") Signed-off-by: Oleksii Kurochko Reviewed-by: Baptiste Le Duc Acked-by: Jan Beulich --- xen/arch/riscv/include/asm/current.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/riscv/include/asm/current.h b/xen/arch/riscv/include/asm/current.h index 5fbee8182c..78ec52fd8a 100644 --- a/xen/arch/riscv/include/asm/current.h +++ b/xen/arch/riscv/include/asm/current.h @@ -54,7 +54,7 @@ DECLARE_PER_CPU(struct vcpu *, curr_vcpu); #define switch_stack_and_jump(stack, fn) do { \ asm volatile ( \ "mv sp, %0\n" \ - "j " #fn :: "r" (stack), "X" (fn) : "memory" ); \ + "jr %1" :: "r" (stack), "r" (fn) : "memory" ); \ unreachable(); \ } while ( false )