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x86/cpuid: Fix TSXLDTRK definition
TSXLDTRK lives in CPUID leaf 7[0].edx, not 7[0].ecx.
Bit 16 in ecx is LA57.
Fixes: a6d1b55847 ("x86emul: support X{SUS,RES}LDTRK")
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
This commit is contained in:
Andrew Cooper committed
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commit
249e0f1d8f
4 files changed
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@@ -209,7 +209,6 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str)
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{"avx512-vnni", 0x00000007, 0, CPUID_REG_ECX, 11, 1},
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{"avx512-bitalg",0x00000007, 0, CPUID_REG_ECX, 12, 1},
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{"avx512-vpopcntdq",0x00000007,0,CPUID_REG_ECX, 14, 1},
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{"tsxldtrk", 0x00000007, 0, CPUID_REG_ECX, 16, 1},
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{"rdpid", 0x00000007, 0, CPUID_REG_ECX, 22, 1},
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{"cldemote", 0x00000007, 0, CPUID_REG_ECX, 25, 1},
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@@ -220,6 +219,7 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str)
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{"srbds-ctrl", 0x00000007, 0, CPUID_REG_EDX, 9, 1},
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{"md-clear", 0x00000007, 0, CPUID_REG_EDX, 10, 1},
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{"serialize", 0x00000007, 0, CPUID_REG_EDX, 14, 1},
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{"tsxldtrk", 0x00000007, 0, CPUID_REG_EDX, 16, 1},
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{"cet-ibt", 0x00000007, 0, CPUID_REG_EDX, 20, 1},
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{"ibrsb", 0x00000007, 0, CPUID_REG_EDX, 26, 1},
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{"stibp", 0x00000007, 0, CPUID_REG_EDX, 27, 1},
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@@ -128,7 +128,6 @@ static const char *const str_7c0[32] =
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[10] = "vpclmulqdq", [11] = "avx512-vnni",
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[12] = "avx512-bitalg",
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[14] = "avx512-vpopcntdq",
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[16] = "tsxldtrk",
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[22] = "rdpid",
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/* 24 */ [25] = "cldemote",
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@@ -172,7 +171,7 @@ static const char *const str_7d0[32] =
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[10] = "md-clear", [11] = "rtm-always-abort",
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/* 12 */ [13] = "tsx-force-abort",
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[14] = "serialize",
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[16] = "tsxldtrk",
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[18] = "pconfig",
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[20] = "cet-ibt",
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@@ -2000,7 +2000,6 @@ amd_like(const struct x86_emulate_ctxt *ctxt)
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#define vcpu_has_avx512_vnni() (ctxt->cpuid->feat.avx512_vnni)
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#define vcpu_has_avx512_bitalg() (ctxt->cpuid->feat.avx512_bitalg)
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#define vcpu_has_avx512_vpopcntdq() (ctxt->cpuid->feat.avx512_vpopcntdq)
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#define vcpu_has_tsxldtrk() (ctxt->cpuid->feat.tsxldtrk)
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#define vcpu_has_rdpid() (ctxt->cpuid->feat.rdpid)
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#define vcpu_has_movdiri() (ctxt->cpuid->feat.movdiri)
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#define vcpu_has_movdir64b() (ctxt->cpuid->feat.movdir64b)
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@@ -2009,6 +2008,7 @@ amd_like(const struct x86_emulate_ctxt *ctxt)
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#define vcpu_has_avx512_4fmaps() (ctxt->cpuid->feat.avx512_4fmaps)
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#define vcpu_has_avx512_vp2intersect() (ctxt->cpuid->feat.avx512_vp2intersect)
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#define vcpu_has_serialize() (ctxt->cpuid->feat.serialize)
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#define vcpu_has_tsxldtrk() (ctxt->cpuid->feat.tsxldtrk)
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#define vcpu_has_avx_vnni() (ctxt->cpuid->feat.avx_vnni)
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#define vcpu_has_avx512_bf16() (ctxt->cpuid->feat.avx512_bf16)
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@@ -239,7 +239,6 @@ XEN_CPUFEATURE(VPCLMULQDQ, 6*32+10) /*A Vector Carry-less Multiplication Ins
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XEN_CPUFEATURE(AVX512_VNNI, 6*32+11) /*A Vector Neural Network Instrs */
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XEN_CPUFEATURE(AVX512_BITALG, 6*32+12) /*A Support for VPOPCNT[B,W] and VPSHUFBITQMB */
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XEN_CPUFEATURE(AVX512_VPOPCNTDQ, 6*32+14) /*A POPCNT for vectors of DW/QW */
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XEN_CPUFEATURE(TSXLDTRK, 6*32+16) /*a TSX load tracking suspend/resume insns */
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XEN_CPUFEATURE(RDPID, 6*32+22) /*A RDPID instruction */
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XEN_CPUFEATURE(CLDEMOTE, 6*32+25) /*A CLDEMOTE instruction */
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XEN_CPUFEATURE(MOVDIRI, 6*32+27) /*a MOVDIRI instruction */
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@@ -280,6 +279,7 @@ XEN_CPUFEATURE(MD_CLEAR, 9*32+10) /*A VERW clears microarchitectural buffe
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XEN_CPUFEATURE(RTM_ALWAYS_ABORT, 9*32+11) /*! June 2021 TSX defeaturing in microcode. */
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XEN_CPUFEATURE(TSX_FORCE_ABORT, 9*32+13) /* MSR_TSX_FORCE_ABORT.RTM_ABORT */
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XEN_CPUFEATURE(SERIALIZE, 9*32+14) /*a SERIALIZE insn */
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XEN_CPUFEATURE(TSXLDTRK, 9*32+16) /*a TSX load tracking suspend/resume insns */
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XEN_CPUFEATURE(CET_IBT, 9*32+20) /* CET - Indirect Branch Tracking */
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XEN_CPUFEATURE(IBRSB, 9*32+26) /*A IBRS and IBPB support (used by Intel) */
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XEN_CPUFEATURE(STIBP, 9*32+27) /*A STIBP */
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