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x86/amd: Drop the cpuid_mask_* command line options
As noted in the command line documentation, these are both deprecated since Xen 4.7 (2016), and are not fully effective on AMD CPUs starting from 2011. Not realised at the time of writing the docs was that their use is also incompatible with certain errata workarounds which edit the CPUID MSRs after the levelling defaults are calculated. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Jan Beulich <jbeulich@suse.com> Acked-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
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@@ -11,6 +11,10 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
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### Added
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### Added
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### Removed
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### Removed
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- On x86:
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- The cpuid_mask_* command line options for legacy AMD CPUs. These were
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deprecated in Xen 4.7 and noted not to work correctly with AMD CPUs from
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2011 onwards.
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## [4.21.0](https://xenbits.xenproject.org/gitweb/?p=xen.git;a=shortlog;h=RELEASE-4.21.0) - 2025-11-19
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## [4.21.0](https://xenbits.xenproject.org/gitweb/?p=xen.git;a=shortlog;h=RELEASE-4.21.0) - 2025-11-19
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@@ -587,46 +587,6 @@ applicable. They can all be ignored.
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in its positive form to override Xen's default behaviour on these systems,
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in its positive form to override Xen's default behaviour on these systems,
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and make the feature fully usable.
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and make the feature fully usable.
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### cpuid_mask_cpu
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> `= fam_0f_rev_[cdefg] | fam_10_rev_[bc] | fam_11_rev_b`
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> Applicability: AMD
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If none of the other **cpuid_mask_\*** options are given, Xen has a set of
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pre-configured masks to make the current processor appear to be
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family/revision specified.
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See below for general information on masking.
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**Warning: This option is not fully effective on Family 15h processors or
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later.**
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### cpuid_mask_ecx
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### cpuid_mask_edx
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### cpuid_mask_ext_ecx
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### cpuid_mask_ext_edx
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### cpuid_mask_l7s0_eax
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### cpuid_mask_l7s0_ebx
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### cpuid_mask_thermal_ecx
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### cpuid_mask_xsave_eax
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> `= <integer>`
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> Applicability: x86. Default: `~0` (all bits set)
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The availability of these options are model specific. Some processors don't
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support any of them, and no processor supports all of them. Xen will ignore
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options on processors which are lacking support.
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These options can be used to alter the features visible via the `CPUID`
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instruction. Settings applied here take effect globally, including for Xen
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and all guests.
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Note: Since Xen 4.7, it is no longer necessary to mask a host to create
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migration safety in heterogeneous scenarios. All necessary CPUID settings
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should be provided in the VM configuration file. Furthermore, it is
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recommended not to use this option, as doing so causes an unnecessary
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reduction of features at Xen's disposal to manage guests.
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### cpuidle (x86)
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### cpuidle (x86)
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> `= <boolean>`
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> `= <boolean>`
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@@ -20,32 +20,6 @@
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#include "cpu.h"
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#include "cpu.h"
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/*
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* Pre-canned values for overriding the CPUID features
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* and extended features masks.
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*
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* Currently supported processors:
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*
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* "fam_0f_rev_c"
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* "fam_0f_rev_d"
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* "fam_0f_rev_e"
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* "fam_0f_rev_f"
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* "fam_0f_rev_g"
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* "fam_10_rev_b"
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* "fam_10_rev_c"
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* "fam_11_rev_b"
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*/
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static char __initdata opt_famrev[14];
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string_param("cpuid_mask_cpu", opt_famrev);
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static unsigned int __initdata opt_cpuid_mask_l7s0_eax = ~0u;
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integer_param("cpuid_mask_l7s0_eax", opt_cpuid_mask_l7s0_eax);
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static unsigned int __initdata opt_cpuid_mask_l7s0_ebx = ~0u;
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integer_param("cpuid_mask_l7s0_ebx", opt_cpuid_mask_l7s0_ebx);
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static unsigned int __initdata opt_cpuid_mask_thermal_ecx = ~0u;
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integer_param("cpuid_mask_thermal_ecx", opt_cpuid_mask_thermal_ecx);
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/* 1 = allow, 0 = don't allow guest creation, -1 = don't allow boot */
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/* 1 = allow, 0 = don't allow guest creation, -1 = don't allow boot */
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int8_t __read_mostly opt_allow_unsafe;
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int8_t __read_mostly opt_allow_unsafe;
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boolean_param("allow_unsafe", opt_allow_unsafe);
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boolean_param("allow_unsafe", opt_allow_unsafe);
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@@ -114,51 +88,6 @@ static void wrmsr_amd(unsigned int msr, uint64_t val)
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"d" (val >> 32), "D" (0x9c5a203a));
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"d" (val >> 32), "D" (0x9c5a203a));
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}
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}
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static const struct cpuidmask {
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uint16_t fam;
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char rev[2];
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unsigned int ecx, edx, ext_ecx, ext_edx;
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} pre_canned[] __initconst = {
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#define CAN(fam, id, rev) { \
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fam, #rev, \
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AMD_FEATURES_##id##_REV_##rev##_ECX, \
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AMD_FEATURES_##id##_REV_##rev##_EDX, \
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AMD_EXTFEATURES_##id##_REV_##rev##_ECX, \
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AMD_EXTFEATURES_##id##_REV_##rev##_EDX \
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}
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#define CAN_FAM(fam, rev) CAN(0x##fam, FAM##fam##h, rev)
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#define CAN_K8(rev) CAN(0x0f, K8, rev)
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CAN_FAM(11, B),
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CAN_FAM(10, C),
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CAN_FAM(10, B),
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CAN_K8(G),
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CAN_K8(F),
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CAN_K8(E),
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CAN_K8(D),
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CAN_K8(C)
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#undef CAN
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};
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static const struct cpuidmask *__init noinline get_cpuidmask(const char *opt)
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{
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unsigned long fam;
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char rev;
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unsigned int i;
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if (strncmp(opt, "fam_", 4))
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return NULL;
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fam = simple_strtoul(opt + 4, &opt, 16);
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if (strncmp(opt, "_rev_", 5) || !opt[5] || opt[6])
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return NULL;
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rev = toupper(opt[5]);
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for (i = 0; i < ARRAY_SIZE(pre_canned); ++i)
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if (fam == pre_canned[i].fam && rev == *pre_canned[i].rev)
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return &pre_canned[i];
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return NULL;
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}
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/*
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/*
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* Sets caps in expected_levelling_cap, probes for the specified mask MSR, and
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* Sets caps in expected_levelling_cap, probes for the specified mask MSR, and
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* set caps in levelling_caps if it is found. Processors prior to Fam 10h
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* set caps in levelling_caps if it is found. Processors prior to Fam 10h
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@@ -295,8 +224,6 @@ static const typeof(ctxt_switch_masking) __initconst_cf_clobber __used csm =
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*/
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*/
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static void __init noinline amd_init_levelling(void)
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static void __init noinline amd_init_levelling(void)
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{
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{
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const struct cpuidmask *m = NULL;
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/*
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/*
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* If there's support for CpuidUserDis or CPUID faulting then
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* If there's support for CpuidUserDis or CPUID faulting then
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* we can skip levelling because CPUID accesses are trapped anyway.
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* we can skip levelling because CPUID accesses are trapped anyway.
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@@ -318,26 +245,11 @@ static void __init noinline amd_init_levelling(void)
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probe_masking_msrs();
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probe_masking_msrs();
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if (*opt_famrev != '\0') {
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m = get_cpuidmask(opt_famrev);
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if (!m)
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printk("Invalid processor string: %s\n", opt_famrev);
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}
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if ((levelling_caps & LCAP_1cd) == LCAP_1cd) {
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if ((levelling_caps & LCAP_1cd) == LCAP_1cd) {
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uint32_t ecx, edx, tmp;
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uint32_t ecx, edx, tmp;
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cpuid(0x00000001, &tmp, &tmp, &ecx, &edx);
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cpuid(0x00000001, &tmp, &tmp, &ecx, &edx);
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if (~(opt_cpuid_mask_ecx & opt_cpuid_mask_edx)) {
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ecx &= opt_cpuid_mask_ecx;
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edx &= opt_cpuid_mask_edx;
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} else if (m) {
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ecx &= m->ecx;
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edx &= m->edx;
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}
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/* Fast-forward bits - Must be set. */
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/* Fast-forward bits - Must be set. */
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if (ecx & cpufeat_mask(X86_FEATURE_XSAVE))
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if (ecx & cpufeat_mask(X86_FEATURE_XSAVE))
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ecx |= cpufeat_mask(X86_FEATURE_OSXSAVE);
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ecx |= cpufeat_mask(X86_FEATURE_OSXSAVE);
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@@ -351,14 +263,6 @@ static void __init noinline amd_init_levelling(void)
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cpuid(0x80000001, &tmp, &tmp, &ecx, &edx);
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cpuid(0x80000001, &tmp, &tmp, &ecx, &edx);
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if (~(opt_cpuid_mask_ext_ecx & opt_cpuid_mask_ext_edx)) {
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ecx &= opt_cpuid_mask_ext_ecx;
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edx &= opt_cpuid_mask_ext_edx;
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} else if (m) {
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ecx &= m->ext_ecx;
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edx &= m->ext_edx;
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}
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/* Fast-forward bits - Must be set. */
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/* Fast-forward bits - Must be set. */
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edx |= cpufeat_mask(X86_FEATURE_APIC);
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edx |= cpufeat_mask(X86_FEATURE_APIC);
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@@ -370,20 +274,12 @@ static void __init noinline amd_init_levelling(void)
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cpuid(0x00000007, &eax, &ebx, &tmp, &tmp);
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cpuid(0x00000007, &eax, &ebx, &tmp, &tmp);
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if (~(opt_cpuid_mask_l7s0_eax & opt_cpuid_mask_l7s0_ebx)) {
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eax &= opt_cpuid_mask_l7s0_eax;
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ebx &= opt_cpuid_mask_l7s0_ebx;
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}
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cpuidmask_defaults._7ab0 &= ((uint64_t)eax << 32) | ebx;
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cpuidmask_defaults._7ab0 &= ((uint64_t)eax << 32) | ebx;
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}
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}
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if ((levelling_caps & LCAP_6c) == LCAP_6c) {
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if ((levelling_caps & LCAP_6c) == LCAP_6c) {
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uint32_t ecx = cpuid_ecx(6);
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uint32_t ecx = cpuid_ecx(6);
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if (~opt_cpuid_mask_thermal_ecx)
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ecx &= opt_cpuid_mask_thermal_ecx;
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cpuidmask_defaults._6c &= (~0ULL << 32) | ecx;
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cpuidmask_defaults._6c &= (~0ULL << 32) | ecx;
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}
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}
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@@ -7,96 +7,6 @@
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#include <asm/cpufeature.h>
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#include <asm/cpufeature.h>
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/* CPUID masked for use by AMD-V Extended Migration */
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/* Family 0Fh, Revision C */
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#define AMD_FEATURES_K8_REV_C_ECX 0
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#define AMD_FEATURES_K8_REV_C_EDX ( \
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cpufeat_mask(X86_FEATURE_FPU) | cpufeat_mask(X86_FEATURE_VME) | \
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cpufeat_mask(X86_FEATURE_DE) | cpufeat_mask(X86_FEATURE_PSE) | \
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cpufeat_mask(X86_FEATURE_TSC) | cpufeat_mask(X86_FEATURE_MSR) | \
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cpufeat_mask(X86_FEATURE_PAE) | cpufeat_mask(X86_FEATURE_MCE) | \
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cpufeat_mask(X86_FEATURE_CX8) | cpufeat_mask(X86_FEATURE_APIC) | \
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cpufeat_mask(X86_FEATURE_SEP) | cpufeat_mask(X86_FEATURE_MTRR) | \
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cpufeat_mask(X86_FEATURE_PGE) | cpufeat_mask(X86_FEATURE_MCA) | \
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cpufeat_mask(X86_FEATURE_CMOV) | cpufeat_mask(X86_FEATURE_PAT) | \
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cpufeat_mask(X86_FEATURE_PSE36) | cpufeat_mask(X86_FEATURE_CLFLUSH)| \
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cpufeat_mask(X86_FEATURE_MMX) | cpufeat_mask(X86_FEATURE_FXSR) | \
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cpufeat_mask(X86_FEATURE_SSE) | cpufeat_mask(X86_FEATURE_SSE2))
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#define AMD_EXTFEATURES_K8_REV_C_ECX 0
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#define AMD_EXTFEATURES_K8_REV_C_EDX ( \
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cpufeat_mask(X86_FEATURE_FPU) | cpufeat_mask(X86_FEATURE_VME) | \
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cpufeat_mask(X86_FEATURE_DE) | cpufeat_mask(X86_FEATURE_PSE) | \
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cpufeat_mask(X86_FEATURE_TSC) | cpufeat_mask(X86_FEATURE_MSR) | \
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cpufeat_mask(X86_FEATURE_PAE) | cpufeat_mask(X86_FEATURE_MCE) | \
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cpufeat_mask(X86_FEATURE_CX8) | cpufeat_mask(X86_FEATURE_APIC) | \
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cpufeat_mask(X86_FEATURE_SYSCALL) | cpufeat_mask(X86_FEATURE_MTRR) | \
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cpufeat_mask(X86_FEATURE_PGE) | cpufeat_mask(X86_FEATURE_MCA) | \
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cpufeat_mask(X86_FEATURE_CMOV) | cpufeat_mask(X86_FEATURE_PAT) | \
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cpufeat_mask(X86_FEATURE_PSE36) | cpufeat_mask(X86_FEATURE_NX) | \
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cpufeat_mask(X86_FEATURE_MMXEXT) | cpufeat_mask(X86_FEATURE_MMX) | \
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cpufeat_mask(X86_FEATURE_FXSR) | cpufeat_mask(X86_FEATURE_LM) | \
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cpufeat_mask(X86_FEATURE_3DNOWEXT) | cpufeat_mask(X86_FEATURE_3DNOW))
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/* Family 0Fh, Revision D */
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#define AMD_FEATURES_K8_REV_D_ECX AMD_FEATURES_K8_REV_C_ECX
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#define AMD_FEATURES_K8_REV_D_EDX AMD_FEATURES_K8_REV_C_EDX
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#define AMD_EXTFEATURES_K8_REV_D_ECX (AMD_EXTFEATURES_K8_REV_C_ECX |\
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cpufeat_mask(X86_FEATURE_LAHF_LM))
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#define AMD_EXTFEATURES_K8_REV_D_EDX (AMD_EXTFEATURES_K8_REV_C_EDX |\
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cpufeat_mask(X86_FEATURE_FFXSR))
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/* Family 0Fh, Revision E */
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#define AMD_FEATURES_K8_REV_E_ECX (AMD_FEATURES_K8_REV_D_ECX | \
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cpufeat_mask(X86_FEATURE_SSE3))
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#define AMD_FEATURES_K8_REV_E_EDX (AMD_FEATURES_K8_REV_D_EDX | \
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cpufeat_mask(X86_FEATURE_HTT))
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#define AMD_EXTFEATURES_K8_REV_E_ECX (AMD_EXTFEATURES_K8_REV_D_ECX |\
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cpufeat_mask(X86_FEATURE_CMP_LEGACY))
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#define AMD_EXTFEATURES_K8_REV_E_EDX AMD_EXTFEATURES_K8_REV_D_EDX
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/* Family 0Fh, Revision F */
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#define AMD_FEATURES_K8_REV_F_ECX (AMD_FEATURES_K8_REV_E_ECX | \
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cpufeat_mask(X86_FEATURE_CX16))
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#define AMD_FEATURES_K8_REV_F_EDX AMD_FEATURES_K8_REV_E_EDX
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#define AMD_EXTFEATURES_K8_REV_F_ECX (AMD_EXTFEATURES_K8_REV_E_ECX |\
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cpufeat_mask(X86_FEATURE_SVM) | cpufeat_mask(X86_FEATURE_EXTAPIC) | \
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cpufeat_mask(X86_FEATURE_CR8_LEGACY))
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#define AMD_EXTFEATURES_K8_REV_F_EDX (AMD_EXTFEATURES_K8_REV_E_EDX |\
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cpufeat_mask(X86_FEATURE_RDTSCP))
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/* Family 0Fh, Revision G */
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#define AMD_FEATURES_K8_REV_G_ECX AMD_FEATURES_K8_REV_F_ECX
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#define AMD_FEATURES_K8_REV_G_EDX AMD_FEATURES_K8_REV_F_EDX
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#define AMD_EXTFEATURES_K8_REV_G_ECX (AMD_EXTFEATURES_K8_REV_F_ECX |\
|
|
||||||
cpufeat_mask(X86_FEATURE_3DNOWPREFETCH))
|
|
||||||
#define AMD_EXTFEATURES_K8_REV_G_EDX AMD_EXTFEATURES_K8_REV_F_EDX
|
|
||||||
|
|
||||||
/* Family 10h, Revision B */
|
|
||||||
#define AMD_FEATURES_FAM10h_REV_B_ECX (AMD_FEATURES_K8_REV_F_ECX | \
|
|
||||||
cpufeat_mask(X86_FEATURE_POPCNT) | cpufeat_mask(X86_FEATURE_MONITOR))
|
|
||||||
#define AMD_FEATURES_FAM10h_REV_B_EDX AMD_FEATURES_K8_REV_F_EDX
|
|
||||||
#define AMD_EXTFEATURES_FAM10h_REV_B_ECX (AMD_EXTFEATURES_K8_REV_F_ECX |\
|
|
||||||
cpufeat_mask(X86_FEATURE_ABM) | cpufeat_mask(X86_FEATURE_SSE4A) | \
|
|
||||||
cpufeat_mask(X86_FEATURE_MISALIGNSSE) | cpufeat_mask(X86_FEATURE_OSVW) |\
|
|
||||||
cpufeat_mask(X86_FEATURE_IBS))
|
|
||||||
#define AMD_EXTFEATURES_FAM10h_REV_B_EDX (AMD_EXTFEATURES_K8_REV_F_EDX |\
|
|
||||||
cpufeat_mask(X86_FEATURE_PAGE1GB))
|
|
||||||
|
|
||||||
/* Family 10h, Revision C */
|
|
||||||
#define AMD_FEATURES_FAM10h_REV_C_ECX AMD_FEATURES_FAM10h_REV_B_ECX
|
|
||||||
#define AMD_FEATURES_FAM10h_REV_C_EDX AMD_FEATURES_FAM10h_REV_B_EDX
|
|
||||||
#define AMD_EXTFEATURES_FAM10h_REV_C_ECX (AMD_EXTFEATURES_FAM10h_REV_B_ECX |\
|
|
||||||
cpufeat_mask(X86_FEATURE_SKINIT) | cpufeat_mask(X86_FEATURE_WDT))
|
|
||||||
#define AMD_EXTFEATURES_FAM10h_REV_C_EDX AMD_EXTFEATURES_FAM10h_REV_B_EDX
|
|
||||||
|
|
||||||
/* Family 11h, Revision B */
|
|
||||||
#define AMD_FEATURES_FAM11h_REV_B_ECX AMD_FEATURES_K8_REV_G_ECX
|
|
||||||
#define AMD_FEATURES_FAM11h_REV_B_EDX AMD_FEATURES_K8_REV_G_EDX
|
|
||||||
#define AMD_EXTFEATURES_FAM11h_REV_B_ECX (AMD_EXTFEATURES_K8_REV_G_ECX |\
|
|
||||||
cpufeat_mask(X86_FEATURE_SKINIT))
|
|
||||||
#define AMD_EXTFEATURES_FAM11h_REV_B_EDX AMD_EXTFEATURES_K8_REV_G_EDX
|
|
||||||
|
|
||||||
/* AMD errata checking
|
/* AMD errata checking
|
||||||
*
|
*
|
||||||
* Errata are defined using the AMD_LEGACY_ERRATUM() or AMD_OSVW_ERRATUM()
|
* Errata are defined using the AMD_LEGACY_ERRATUM() or AMD_OSVW_ERRATUM()
|
||||||
|
|||||||