From 351d41e8aecc3f7566a0baa7b4066d06dedd7113 Mon Sep 17 00:00:00 2001 From: Michal Orzel Date: Fri, 28 Nov 2025 12:49:13 +0100 Subject: [PATCH] vgic-v3: Ignore writes to ISACTIVER{nE}N when eSPI is not used Prior to introducing GICv3 eSPI support, writes to these registers were ignored. Now the behavior is changed and we inject fault to the guests. According to documentation, eSPI registers are treated as RES0, when GICD_TYPER.ESPI is 0 (this would be the case when CONFIG_GICV3_ESPI=n or nr_espis is 0). Restore the previous behavior by checking whether eSPI is in use or not. Fixes: 93eecb2c4b88 ("xen/arm: vgic-v3: add emulation of GICv3.1 eSPI registers") Signed-off-by: Michal Orzel Reviewed-by: Julien Grall --- xen/arch/arm/vgic-v3.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index 8b1c8eef80..77aab5c3c2 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -884,9 +884,18 @@ static int __vgic_v3_distr_common_mmio_write(const char *name, struct vcpu *v, "%pv: %s: unhandled word write %#"PRIregister" to ISACTIVER%d\n", v, name, r, reg - GICD_ISACTIVER); else + { +#ifdef CONFIG_GICV3_ESPI + if ( !v->domain->arch.vgic.nr_espis ) + goto write_ignore; + printk(XENLOG_G_ERR "%pv: %s: unhandled word write %#"PRIregister" to ISACTIVER%dE\n", v, name, r, reg - GICD_ISACTIVERnE); +#else + goto write_ignore; +#endif + } return 0; case VRANGE32(GICD_ICACTIVER, GICD_ICACTIVERN):