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x86/msr: introduce struct msr_vcpu_policy
The new structure contains information about guest's MSRs that are
unique to each vCPU. It starts with only 1 MSR:
MSR_INTEL_MISC_FEATURES_ENABLES
Which currently has only 1 usable bit: cpuid_faulting.
Add 2 global policy objects: hvm_max and pv_max that are inited during
boot up. Availability of MSR_INTEL_MISC_FEATURES_ENABLES depends on
availability of MSR_INTEL_PLATFORM_INFO.
Add init_vcpu_msr_policy() which sets initial MSR policy for every vCPU
during domain creation with a special case for Dom0.
Signed-off-by: Sergey Dyasli <sergey.dyasli@citrix.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
This commit is contained in:
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4 files changed
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@@ -351,13 +351,27 @@ int vcpu_initialise(struct vcpu *v)
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/* Idle domain */
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v->arch.cr3 = __pa(idle_pg_table);
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rc = 0;
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v->arch.msr = ZERO_BLOCK_PTR; /* Catch stray misuses */
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}
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if ( rc )
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vcpu_destroy_fpu(v);
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else if ( !is_idle_domain(v->domain) )
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goto fail;
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if ( !is_idle_domain(v->domain) )
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{
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vpmu_initialise(v);
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if ( (rc = init_vcpu_msr_policy(v)) )
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goto fail;
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}
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return rc;
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fail:
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vcpu_destroy_fpu(v);
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xfree(v->arch.msr);
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v->arch.msr = NULL;
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return rc;
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}
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@@ -27,9 +27,13 @@
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struct msr_domain_policy __read_mostly hvm_max_msr_domain_policy,
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__read_mostly pv_max_msr_domain_policy;
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struct msr_vcpu_policy __read_mostly hvm_max_msr_vcpu_policy,
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__read_mostly pv_max_msr_vcpu_policy;
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static void __init calculate_hvm_max_policy(void)
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{
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struct msr_domain_policy *dp = &hvm_max_msr_domain_policy;
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struct msr_vcpu_policy *vp = &hvm_max_msr_vcpu_policy;
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if ( !hvm_enabled )
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return;
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@@ -40,11 +44,15 @@ static void __init calculate_hvm_max_policy(void)
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dp->plaform_info.available = true;
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dp->plaform_info.cpuid_faulting = true;
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}
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/* 0x00000140 MSR_INTEL_MISC_FEATURES_ENABLES */
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vp->misc_features_enables.available = dp->plaform_info.available;
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}
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static void __init calculate_pv_max_policy(void)
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{
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struct msr_domain_policy *dp = &pv_max_msr_domain_policy;
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struct msr_vcpu_policy *vp = &pv_max_msr_vcpu_policy;
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/* 0x000000ce MSR_INTEL_PLATFORM_INFO */
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if ( cpu_has_cpuid_faulting )
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@@ -52,6 +60,9 @@ static void __init calculate_pv_max_policy(void)
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dp->plaform_info.available = true;
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dp->plaform_info.cpuid_faulting = true;
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}
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/* 0x00000140 MSR_INTEL_MISC_FEATURES_ENABLES */
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vp->misc_features_enables.available = dp->plaform_info.available;
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}
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void __init init_guest_msr_policy(void)
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@@ -84,6 +95,28 @@ int init_domain_msr_policy(struct domain *d)
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return 0;
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}
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int init_vcpu_msr_policy(struct vcpu *v)
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{
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struct domain *d = v->domain;
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struct msr_vcpu_policy *vp;
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vp = xmalloc(struct msr_vcpu_policy);
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if ( !vp )
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return -ENOMEM;
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*vp = is_pv_domain(d) ? pv_max_msr_vcpu_policy :
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hvm_max_msr_vcpu_policy;
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/* See comment in intel_ctxt_switch_levelling() */
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if ( is_control_domain(d) )
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vp->misc_features_enables.available = false;
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v->arch.msr = vp;
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return 0;
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}
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/*
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* Local variables:
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* mode: C
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@@ -577,6 +577,8 @@ struct arch_vcpu
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struct arch_vm_event *vm_event;
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struct msr_vcpu_policy *msr;
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struct {
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bool next_interrupt_enabled;
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} monitor;
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@@ -212,8 +212,19 @@ struct msr_domain_policy
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} plaform_info;
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};
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/* MSR policy object for per-vCPU MSRs */
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struct msr_vcpu_policy
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{
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/* 0x00000140 MSR_INTEL_MISC_FEATURES_ENABLES */
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struct {
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bool available; /* This MSR is non-architectural */
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bool cpuid_faulting;
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} misc_features_enables;
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};
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void init_guest_msr_policy(void);
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int init_domain_msr_policy(struct domain *d);
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int init_vcpu_msr_policy(struct vcpu *v);
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#endif /* !__ASSEMBLY__ */
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