diff --git a/xen/arch/x86/acpi/Makefile b/xen/arch/x86/acpi/Makefile index 1b9e625713..041377e2bb 100644 --- a/xen/arch/x86/acpi/Makefile +++ b/xen/arch/x86/acpi/Makefile @@ -1,4 +1,4 @@ obj-y += cpufreq/ -obj-y += lib.o power.o suspend.o cpu_idle.o cpuidle_menu.o +obj-y += lib.o power.o cpu_idle.o cpuidle_menu.o obj-bin-y += boot.init.o wakeup_prot.o diff --git a/xen/arch/x86/acpi/power.c b/xen/arch/x86/acpi/power.c index 6dfd4c7891..0cda362045 100644 --- a/xen/arch/x86/acpi/power.c +++ b/xen/arch/x86/acpi/power.c @@ -195,7 +195,6 @@ static int enter_state(u32 state) unsigned long flags; int error; struct cpu_info *ci; - unsigned long cr4; if ( (state <= ACPI_STATE_S0) || (state > ACPI_S_STATES_MAX) ) return -EINVAL; @@ -270,15 +269,15 @@ static int enter_state(u32 state) system_state = SYS_STATE_resume; - /* Restore CR4 and EFER from cached values. */ - cr4 = read_cr4(); - write_cr4(cr4 & ~X86_CR4_MCE); + /* Restore EFER from cached value. */ write_efer(read_efer()); device_power_up(SAVED_ALL); mcheck_init(&boot_cpu_data, false); - write_cr4(cr4); + + /* Restore CR4 from cached value, now MCE is set up. */ + write_cr4(read_cr4()); printk(XENLOG_INFO "Finishing wakeup from ACPI S%d state.\n", state); diff --git a/xen/arch/x86/acpi/suspend.c b/xen/arch/x86/acpi/suspend.c deleted file mode 100644 index 3c1a3cbb34..0000000000 --- a/xen/arch/x86/acpi/suspend.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Portions are: - * Copyright (c) 2002 Pavel Machek - * Copyright (c) 2001 Patrick Mochel - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static unsigned long saved_fs_base, saved_gs_base, saved_kernel_gs_base; -static uint64_t saved_xcr0; - -void save_rest_processor_state(void) -{ - saved_fs_base = rdfsbase(); - saved_gs_base = rdgsbase(); - rdmsrl(MSR_SHADOW_GS_BASE, saved_kernel_gs_base); - - if ( cpu_has_xsave ) - saved_xcr0 = get_xcr0(); -} - - -void restore_rest_processor_state(void) -{ - load_system_tables(); - - /* Restore full CR4 (inc MCE) now that the IDT is in place. */ - write_cr4(mmu_cr4_features); - - wrfsbase(saved_fs_base); - wrgsbase(saved_gs_base); - wrmsrl(MSR_SHADOW_GS_BASE, saved_kernel_gs_base); - - if ( cpu_has_xsave && !set_xcr0(saved_xcr0) ) - BUG(); - - wrmsrl(MSR_IA32_CR_PAT, XEN_MSR_PAT); - - mtrr_bp_restore(); -} diff --git a/xen/arch/x86/acpi/wakeup_prot.S b/xen/arch/x86/acpi/wakeup_prot.S index 0ce96e26a9..4dba6020a7 100644 --- a/xen/arch/x86/acpi/wakeup_prot.S +++ b/xen/arch/x86/acpi/wakeup_prot.S @@ -15,8 +15,6 @@ ENTRY(do_suspend_lowlevel) mov %cr0, %rax mov %rax, saved_cr0(%rip) - call save_rest_processor_state - /* enter sleep state physically */ mov $3, %edi call acpi_enter_sleep_state @@ -51,7 +49,7 @@ ENTRY(s3_resume) lretq 1: - call restore_rest_processor_state + call load_system_tables .Lsuspend_err: pop %r15 diff --git a/xen/arch/x86/boot/trampoline.S b/xen/arch/x86/boot/trampoline.S index 18c6638924..662e6bdd3c 100644 --- a/xen/arch/x86/boot/trampoline.S +++ b/xen/arch/x86/boot/trampoline.S @@ -91,6 +91,11 @@ trampoline_protmode_entry: and %edi,%edx wrmsr 1: + /* Set up PAT before enabling paging. */ + mov $XEN_MSR_PAT & 0xffffffff, %eax + mov $XEN_MSR_PAT >> 32, %edx + mov $MSR_IA32_CR_PAT, %ecx + wrmsr /* Set up EFER (Extended Feature Enable Register). */ movl $MSR_EFER,%ecx diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index 1b33f1ed71..2e9631f6b2 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -790,8 +790,6 @@ void cpu_init(void) if (opt_cpu_info) printk("Initializing CPU#%d\n", cpu); - wrmsrl(MSR_IA32_CR_PAT, XEN_MSR_PAT); - /* Install correct page table. */ write_ptbase(current); diff --git a/xen/arch/x86/efi/efi-boot.h b/xen/arch/x86/efi/efi-boot.h index a13304201f..176df20c9c 100644 --- a/xen/arch/x86/efi/efi-boot.h +++ b/xen/arch/x86/efi/efi-boot.h @@ -242,6 +242,7 @@ static void __init noreturn efi_arch_post_exit_boot(void) if ( cpu_has_nx ) efer |= EFER_NX; wrmsrl(MSR_EFER, efer); + wrmsrl(MSR_IA32_CR_PAT, XEN_MSR_PAT); write_cr0(X86_CR0_PE | X86_CR0_MP | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM | X86_CR0_PG); asm volatile ( "mov %[cr4], %%cr4\n\t"