diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c
index fced75a644..462736633b 100644
--- a/xen/arch/arm/setup.c
+++ b/xen/arch/arm/setup.c
@@ -682,18 +682,6 @@ static void __init setup_mm(unsigned long dtb_paddr, size_t dtb_size)
 
 size_t __read_mostly dcache_line_bytes;
 
-/* Very early check of the CPU cache properties */
-void __init setup_cache(void)
-{
-    uint32_t ctr;
-
-    /* Read CTR */
-    ctr = READ_SYSREG32(CTR_EL0);
-
-    /* Bits 16-19 are the log2 number of words in the cacheline. */
-    dcache_line_bytes = (size_t) (4 << ((ctr >> 16) & 0xf));
-}
-
 /* C entry point for boot CPU */
 void __init start_xen(unsigned long boot_phys_offset,
                       unsigned long fdt_paddr,
@@ -707,7 +695,7 @@ void __init start_xen(unsigned long boot_phys_offset,
     struct domain *dom0;
     struct xen_arch_domainconfig config;
 
-    setup_cache();
+    dcache_line_bytes = read_dcache_line_bytes();
 
     percpu_init_areas();
     set_processor_id(0); /* needed early, for smp_processor_id() */
diff --git a/xen/arch/arm/smpboot.c b/xen/arch/arm/smpboot.c
index 04efb335a7..62f795f68e 100644
--- a/xen/arch/arm/smpboot.c
+++ b/xen/arch/arm/smpboot.c
@@ -323,6 +323,14 @@ void start_secondary(unsigned long boot_phys_offset,
         stop_cpu();
     }
 
+    if ( dcache_line_bytes != read_dcache_line_bytes() )
+    {
+        printk(XENLOG_ERR "CPU%u dcache line size (%zu) does not match the boot CPU (%zu)\n",
+               smp_processor_id(), read_dcache_line_bytes(),
+               dcache_line_bytes);
+        stop_cpu();
+    }
+
     mmu_init_secondary_cpu();
 
     gic_init_secondary_cpu();
diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h
index 243aacdaed..bcdea970ca 100644
--- a/xen/include/asm-arm/page.h
+++ b/xen/include/asm-arm/page.h
@@ -138,6 +138,17 @@ extern size_t dcache_line_bytes;
 
 #define copy_page(dp, sp) memcpy(dp, sp, PAGE_SIZE)
 
+static inline size_t read_dcache_line_bytes(void)
+{
+    uint32_t ctr;
+
+    /* Read CTR */
+    ctr = READ_SYSREG32(CTR_EL0);
+
+    /* Bits 16-19 are the log2 number of words in the cacheline. */
+    return (size_t) (4 << ((ctr >> 16) & 0xf));
+}
+
 /* Functions for flushing medium-sized areas.
  * if 'range' is large enough we might want to use model-specific
  * full-cache flushes. */