From 4dd6760706848de30f7c8b5f83462b9bcb070c91 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Date: Tue, 30 Jan 2024 10:13:58 +0100 Subject: [PATCH] x86/spec-ctrl: Expose IPRED_CTRL to guests MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The CPUID feature bit signals the presence of the IPRED_DIS_{U,S} controls in SPEC_CTRL MSR, first available in Intel AlderLake and Sapphire Rapids CPUs. Xen already knows how to context switch MSR_SPEC_CTRL properly between guest and hypervisor context. Signed-off-by: Roger Pau Monné Reviewed-by: Jan Beulich Reviewed-by: Andrew Cooper --- xen/arch/x86/msr.c | 6 ++++-- xen/include/public/arch-x86/cpufeatureset.h | 2 +- xen/tools/gen-cpuid.py | 3 ++- 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index c33dc78cd8..54d3752e93 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -309,8 +309,8 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val) /* * Caller to confirm that MSR_SPEC_CTRL is available. Intel and AMD have - * separate CPUID features for this functionality, but only set will be - * active. + * separate CPUID features for some of this functionality, but only one + * vendors-worth will be active on a single host. */ uint64_t msr_spec_ctrl_valid_bits(const struct cpu_policy *cp) { @@ -324,6 +324,8 @@ uint64_t msr_spec_ctrl_valid_bits(const struct cpu_policy *cp) return (SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | (ssbd ? SPEC_CTRL_SSBD : 0) | (psfd ? SPEC_CTRL_PSFD : 0) | + (cp->feat.ipred_ctrl + ? (SPEC_CTRL_IPRED_DIS_U | SPEC_CTRL_IPRED_DIS_S) : 0) | 0); } diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h index c897c20401..e586e141c3 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -302,7 +302,7 @@ XEN_CPUFEATURE(INTEL_PPIN, 12*32+ 0) /* Protected Processor Inventory /* Intel-defined CPU features, CPUID level 0x00000007:2.edx, word 13 */ XEN_CPUFEATURE(INTEL_PSFD, 13*32+ 0) /*A MSR_SPEC_CTRL.PSFD */ -XEN_CPUFEATURE(IPRED_CTRL, 13*32+ 1) /* MSR_SPEC_CTRL.IPRED_DIS_* */ +XEN_CPUFEATURE(IPRED_CTRL, 13*32+ 1) /*A MSR_SPEC_CTRL.IPRED_DIS_* */ XEN_CPUFEATURE(RRSBA_CTRL, 13*32+ 2) /* MSR_SPEC_CTRL.RRSBA_DIS_* */ XEN_CPUFEATURE(DDP_CTRL, 13*32+ 3) /* MSR_SPEC_CTRL.DDP_DIS_U */ XEN_CPUFEATURE(BHI_CTRL, 13*32+ 4) /* MSR_SPEC_CTRL.BHI_DIS_S */ diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py index df5222a3cd..45fab5e75d 100755 --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -319,7 +319,8 @@ def crunch_numbers(state): # IBRSB/IBRS, and we pass this MSR directly to guests. Treating them # as dependent features simplifies Xen's logic, and prevents the guest # from seeing implausible configurations. - IBRSB: [STIBP, SSBD, INTEL_PSFD, EIBRS], + IBRSB: [STIBP, SSBD, INTEL_PSFD, EIBRS, + IPRED_CTRL], IBRS: [AMD_STIBP, AMD_SSBD, PSFD, AUTO_IBRS, IBRS_ALWAYS, IBRS_FAST, IBRS_SAME_MODE], IBPB: [IBPB_RET, SBPB, IBPB_BRTYPE],