diff --git a/xen/arch/arm/include/asm/processor.h b/xen/arch/arm/include/asm/processor.h
index a3753c317f..509040a1cd 100644
--- a/xen/arch/arm/include/asm/processor.h
+++ b/xen/arch/arm/include/asm/processor.h
@@ -521,6 +521,7 @@ extern register_t __cpu_logical_map[];
 /*
  * 543210 BIT
  * 00XXLL -- XX Fault Level LL
+ * ..00LL -- Address Size Fault LL
  * ..01LL -- Translation Fault LL
  * ..10LL -- Access Fault LL
  * ..11LL -- Permission Fault LL
@@ -534,6 +535,7 @@ extern register_t __cpu_logical_map[];
 #define FSC_TYPE_OTH   (_AC(0x02,U)<<4)
 #define FSC_TYPE_IMPL  (_AC(0x03,U)<<4)
 
+#define FSC_FLT_ADDR_SIZE (0x00)
 #define FSC_FLT_TRANS  (0x04)
 #define FSC_FLT_ACCESS (0x08)
 #define FSC_FLT_PERM   (0x0c)
diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index 0c01f37ad6..344aa21b98 100644
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/traps.c
@@ -307,6 +307,10 @@ static const char *decode_fsc(uint32_t fsc, int *level)
 
     switch ( fsc & 0x3f )
     {
+    case FSC_FLT_ADDR_SIZE ... FSC_FLT_ADDR_SIZE + 3:
+        msg = "Address size fault";
+        *level = fsc & FSC_LL_MASK;
+        break;
     case FSC_FLT_TRANS ... FSC_FLT_TRANS + 3:
         msg = "Translation fault";
         *level = fsc & FSC_LL_MASK;
@@ -363,6 +367,7 @@ static const char *fsc_level_str(int level)
     switch ( level )
     {
     case -1: return "";
+    case 0:  return " at level 0 or TTBR";
     case 1:  return " at level 1";
     case 2:  return " at level 2";
     case 3:  return " at level 3";