diff --git a/CHANGELOG.md b/CHANGELOG.md
index 7de34f64d1..53d92a2597 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -12,9 +12,9 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
 
 ### Removed
  - On x86:
-   - The cpuid_mask_* command line options for legacy AMD CPUs.  These were
+   - The cpuid_mask_* command line options for legacy CPUs.  These were
      deprecated in Xen 4.7 and noted not to work correctly with AMD CPUs from
-     2011 onwards.
+     2011 onwards, nor work at all with Intel CPUs from 2012.
    - Xenoprofile support.  Oprofile themselves removed support for Xen in 2014
      prior to the version 1.0 release, and there has been no development since
      before then in Xen.
diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
index 091c018934..28aca3417d 100644
--- a/xen/arch/x86/cpu/common.c
+++ b/xen/arch/x86/cpu/common.c
@@ -31,19 +31,6 @@ bool __read_mostly opt_dom0_cpuid_faulting = true;
 bool opt_arat = true;
 boolean_param("arat", opt_arat);
 
-unsigned int opt_cpuid_mask_ecx = ~0u;
-integer_param("cpuid_mask_ecx", opt_cpuid_mask_ecx);
-unsigned int opt_cpuid_mask_edx = ~0u;
-integer_param("cpuid_mask_edx", opt_cpuid_mask_edx);
-
-unsigned int opt_cpuid_mask_xsave_eax = ~0u;
-integer_param("cpuid_mask_xsave_eax", opt_cpuid_mask_xsave_eax);
-
-unsigned int opt_cpuid_mask_ext_ecx = ~0u;
-integer_param("cpuid_mask_ext_ecx", opt_cpuid_mask_ext_ecx);
-unsigned int opt_cpuid_mask_ext_edx = ~0u;
-integer_param("cpuid_mask_ext_edx", opt_cpuid_mask_ext_edx);
-
 unsigned int __initdata expected_levelling_cap;
 unsigned int __read_mostly levelling_caps;
 
diff --git a/xen/arch/x86/cpu/cpu.h b/xen/arch/x86/cpu/cpu.h
index 8bed3f5249..bbede57ab0 100644
--- a/xen/arch/x86/cpu/cpu.h
+++ b/xen/arch/x86/cpu/cpu.h
@@ -12,9 +12,6 @@ extern const struct cpu_dev intel_cpu_dev, amd_cpu_dev, centaur_cpu_dev,
     shanghai_cpu_dev, hygon_cpu_dev;
 
 extern bool opt_arat;
-extern unsigned int opt_cpuid_mask_ecx, opt_cpuid_mask_edx;
-extern unsigned int opt_cpuid_mask_xsave_eax;
-extern unsigned int opt_cpuid_mask_ext_ecx, opt_cpuid_mask_ext_edx;
 
 extern int get_model_name(struct cpuinfo_x86 *c);
 extern void display_cacheinfo(struct cpuinfo_x86 *c);
diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c
index 7037f1f268..584588e406 100644
--- a/xen/arch/x86/cpu/intel.c
+++ b/xen/arch/x86/cpu/intel.c
@@ -251,14 +251,10 @@ static const typeof(ctxt_switch_masking) __initconst_cf_clobber __used csm =
     intel_ctxt_switch_masking;
 #endif
 
-/*
- * opt_cpuid_mask_ecx/edx: cpuid.1[ecx, edx] feature mask.
- * For example, E8400[Intel Core 2 Duo Processor series] ecx = 0x0008E3FD,
- * edx = 0xBFEBFBFF when executing CPUID.EAX = 1 normally. If you want to
- * 'rev down' to E8400, you can set these values in these Xen boot parameters.
- */
 static void __init noinline intel_init_levelling(void)
 {
+	uint32_t eax, ecx, edx, tmp;
+
 	/*
 	 * Intel Fam0f is old enough that probing for CPUID faulting support
 	 * introduces spurious #GP(0) when the appropriate MSRs are read,
@@ -275,13 +271,8 @@ static void __init noinline intel_init_levelling(void)
 	probe_masking_msrs();
 
 	if (msr_basic) {
-		uint32_t ecx, edx, tmp;
-
 		cpuid(0x00000001, &tmp, &tmp, &ecx, &edx);
 
-		ecx &= opt_cpuid_mask_ecx;
-		edx &= opt_cpuid_mask_edx;
-
 		/* Fast-forward bits - Must be set. */
 		if (ecx & cpufeat_mask(X86_FEATURE_XSAVE))
 			ecx |= cpufeat_mask(X86_FEATURE_OSXSAVE);
@@ -291,23 +282,12 @@ static void __init noinline intel_init_levelling(void)
 	}
 
 	if (msr_ext) {
-		uint32_t ecx, edx, tmp;
-
 		cpuid(0x80000001, &tmp, &tmp, &ecx, &edx);
-
-		ecx &= opt_cpuid_mask_ext_ecx;
-		edx &= opt_cpuid_mask_ext_edx;
-
 		cpuidmask_defaults.e1cd &= ((u64)edx << 32) | ecx;
 	}
 
 	if (msr_xsave) {
-		uint32_t eax, tmp;
-
 		cpuid_count(0x0000000d, 1, &eax, &tmp, &tmp, &tmp);
-
-		eax &= opt_cpuid_mask_xsave_eax;
-
 		cpuidmask_defaults.Da1 &= (~0ULL << 32) | eax;
 	}