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arch/arm: let map_mmio_regions() take pfn as parameters

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Currently, the map_mmio_regions() function, defined for the ARM
architecture, has parameters with paddr_t type. This interface,
however, needs caller functions to correctly page-align addresses
given as parameters to map_mmio_regions(). This commit changes the
function's interface to accept page frame numbers as parameters.
This commit also modifies caller functions in an attempt to adapt
them to the new interface.
This commit is meant to produce the minimum indispensable needed
changes; these are also instrumental to making the interface of
map_mmio_regions() symmetric with the unmap_mmio_regions() function,
that will be introduced in one of the next commits of the series
and will feature a pfn-based interface.

NOTE: platform-specific code has not been tested, save for the
      sunxi and the Arndale Exynos 5 platforms (see the Tested-by
      below for the latter).

Signed-off-by: Arianna Avanzini <avanzini.arianna@gmail.com>
Tested-by: Julien Grall <julien.grall@citrix.com>
Acked-by: Ian Campbell <Ian.Campbell@eu.citrix.com>
Cc: Dario Faggioli <dario.faggioli@citrix.com>
Cc: Paolo Valente <paolo.valente@unimore.it>
Cc: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Cc: Jan Beulich <JBeulich@suse.com>
Cc: Keir Fraser <keir@xen.org>
Cc: Tim Deegan <tim@xen.org>
Cc: Ian Jackson <Ian.Jackson@eu.citrix.com>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: Eric Trudeau <etrudeau@broadcom.com>
Cc: Viktor Kleinik <viktor.kleinik@globallogic.com>
This commit is contained in:
Arianna Avanzini authored and Ian Campbell committed 2014-07-18 13:38:08 +01:00
1 parent 2a8cc1a553
commit 59bb589096
8 files changed
+52 -37
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xen/arch/arm/domain_build.c
+4 -3
View File
@@ -1018,9 +1018,10 @@ static int map_device(struct domain *d, struct dt_device_node *dev)
addr & PAGE_MASK, PAGE_ALIGN(addr + size) - 1);
return res;
}
res = map_mmio_regions(d, addr & PAGE_MASK,
PAGE_ALIGN(addr + size) - 1,
addr & PAGE_MASK);
res = map_mmio_regions(d,
paddr_to_pfn(addr & PAGE_MASK),
paddr_to_pfn_aligned(addr + size),
paddr_to_pfn(addr & PAGE_MASK));
if ( res )
{
printk(XENLOG_ERR "Unable to map 0x%"PRIx64
xen/arch/arm/gic-v2.c
+11 -9
View File
@@ -440,20 +440,22 @@ static int gicv2v_setup(struct domain *d)
* The second page is always mapped at +4K irrespective of the
* GIC_64K_STRIDE quirk. The DTB passed to the guest reflects this.
*/
ret = map_mmio_regions(d, d->arch.vgic.cbase,
d->arch.vgic.cbase + PAGE_SIZE - 1,
gicv2.vbase);
ret = map_mmio_regions(d, paddr_to_pfn(d->arch.vgic.cbase),
paddr_to_pfn_aligned(d->arch.vgic.cbase + PAGE_SIZE),
paddr_to_pfn(gicv2.vbase));
if ( ret )
return ret;
if ( !platform_has_quirk(PLATFORM_QUIRK_GIC_64K_STRIDE) )
ret = map_mmio_regions(d, d->arch.vgic.cbase + PAGE_SIZE,
d->arch.vgic.cbase + (2 * PAGE_SIZE) - 1,
gicv2.vbase + PAGE_SIZE);
ret = map_mmio_regions(d, paddr_to_pfn(d->arch.vgic.cbase + PAGE_SIZE),
paddr_to_pfn_aligned(d->arch.vgic.cbase +
(2 * PAGE_SIZE)),
paddr_to_pfn(gicv2.vbase + PAGE_SIZE));
else
ret = map_mmio_regions(d, d->arch.vgic.cbase + PAGE_SIZE,
d->arch.vgic.cbase + (2 * PAGE_SIZE) - 1,
gicv2.vbase + 16*PAGE_SIZE);
ret = map_mmio_regions(d, paddr_to_pfn(d->arch.vgic.cbase + PAGE_SIZE),
paddr_to_pfn_aligned(d->arch.vgic.cbase +
(2 * PAGE_SIZE)),
paddr_to_pfn(gicv2.vbase + 16*PAGE_SIZE));
return ret;
}
xen/arch/arm/p2m.c
+8 -5
View File
@@ -813,12 +813,15 @@ int p2m_populate_ram(struct domain *d,
}
int map_mmio_regions(struct domain *d,
paddr_t start_gaddr,
paddr_t end_gaddr,
paddr_t maddr)
unsigned long start_gfn,
unsigned long end_gfn,
unsigned long mfn)
{
return apply_p2m_changes(d, INSERT, start_gaddr, end_gaddr,
maddr, MATTR_DEV, p2m_mmio_direct);
return apply_p2m_changes(d, INSERT,
pfn_to_paddr(start_gfn),
pfn_to_paddr(end_gfn),
pfn_to_paddr(mfn),
MATTR_DEV, p2m_mmio_direct);
}
int guest_physmap_add_entry(struct domain *d,
xen/arch/arm/platforms/exynos5.c
+6 -5
View File
@@ -54,13 +54,14 @@ static int exynos5_init_time(void)
static int exynos5_specific_mapping(struct domain *d)
{
/* Map the chip ID */
map_mmio_regions(d, EXYNOS5_PA_CHIPID, EXYNOS5_PA_CHIPID + PAGE_SIZE - 1,
EXYNOS5_PA_CHIPID);
map_mmio_regions(d, paddr_to_pfn(EXYNOS5_PA_CHIPID),
paddr_to_pfn_aligned(EXYNOS5_PA_CHIPID + PAGE_SIZE),
paddr_to_pfn(EXYNOS5_PA_CHIPID));
/* Map the PWM region */
map_mmio_regions(d, EXYNOS5_PA_TIMER,
EXYNOS5_PA_TIMER + (PAGE_SIZE * 2) - 1,
EXYNOS5_PA_TIMER);
map_mmio_regions(d, paddr_to_pfn(EXYNOS5_PA_TIMER),
paddr_to_pfn_aligned(EXYNOS5_PA_TIMER + (PAGE_SIZE * 2)),
paddr_to_pfn(EXYNOS5_PA_TIMER));
return 0;
}
xen/arch/arm/platforms/omap5.c
+12 -9
View File
@@ -102,21 +102,24 @@ static int omap5_init_time(void)
static int omap5_specific_mapping(struct domain *d)
{
/* Map the PRM module */
map_mmio_regions(d, OMAP5_PRM_BASE, OMAP5_PRM_BASE + (PAGE_SIZE * 2) - 1,
OMAP5_PRM_BASE);
map_mmio_regions(d, paddr_to_pfn(OMAP5_PRM_BASE),
paddr_to_pfn_aligned(OMAP5_PRM_BASE + (PAGE_SIZE * 2)),
paddr_to_pfn(OMAP5_PRM_BASE));
/* Map the PRM_MPU */
map_mmio_regions(d, OMAP5_PRCM_MPU_BASE,
OMAP5_PRCM_MPU_BASE + PAGE_SIZE - 1,
OMAP5_PRCM_MPU_BASE);
map_mmio_regions(d, paddr_to_pfn(OMAP5_PRCM_MPU_BASE),
paddr_to_pfn_aligned(OMAP5_PRCM_MPU_BASE + PAGE_SIZE),
paddr_to_pfn(OMAP5_PRCM_MPU_BASE));
/* Map the Wakeup Gen */
map_mmio_regions(d, OMAP5_WKUPGEN_BASE, OMAP5_WKUPGEN_BASE + PAGE_SIZE - 1,
OMAP5_WKUPGEN_BASE);
map_mmio_regions(d, paddr_to_pfn(OMAP5_WKUPGEN_BASE),
paddr_to_pfn_aligned(OMAP5_WKUPGEN_BASE + PAGE_SIZE),
paddr_to_pfn(OMAP5_WKUPGEN_BASE));
/* Map the on-chip SRAM */
map_mmio_regions(d, OMAP5_SRAM_PA, OMAP5_SRAM_PA + (PAGE_SIZE * 32) - 1,
OMAP5_SRAM_PA);
map_mmio_regions(d, paddr_to_pfn(OMAP5_SRAM_PA),
paddr_to_pfn_aligned(OMAP5_SRAM_PA + (PAGE_SIZE * 32)),
paddr_to_pfn(OMAP5_SRAM_PA));
return 0;
}
xen/arch/arm/platforms/xgene-storm.c
+3 -1
View File
@@ -47,7 +47,9 @@ static int map_one_mmio(struct domain *d, const char *what,
printk("Additional MMIO %"PRIpaddr"-%"PRIpaddr" (%s)\n",
start, end, what);
ret = map_mmio_regions(d, start, end, start);
ret = map_mmio_regions(d, paddr_to_pfn(start),
paddr_to_pfn_aligned(end),
paddr_to_pfn(start));
if ( ret )
printk("Failed to map %s @ %"PRIpaddr" to dom%d\n",
what, start, d->domain_id);
xen/include/asm-arm/mm.h
+2
View File
@@ -210,6 +210,8 @@ static inline void __iomem *ioremap_wc(paddr_t start, size_t len)
#define paddr_to_pfn(pa) ((unsigned long)((pa) >> PAGE_SHIFT))
#define paddr_to_pdx(pa) pfn_to_pdx(paddr_to_pfn(pa))
/* Page-align address and convert to frame number format */
#define paddr_to_pfn_aligned(paddr) paddr_to_pfn(PAGE_ALIGN(paddr))
static inline paddr_t __virt_to_maddr(vaddr_t va)
{
xen/include/asm-arm/p2m.h
+6 -5
View File
@@ -99,11 +99,12 @@ int p2m_cache_flush(struct domain *d, xen_pfn_t start_mfn, xen_pfn_t end_mfn);
/* Setup p2m RAM mapping for domain d from start-end. */
int p2m_populate_ram(struct domain *d, paddr_t start, paddr_t end);
/* Map MMIO regions in the p2m: start_gaddr and end_gaddr is the range
* in the guest physical address space to map, starting from the machine
* address maddr. */
int map_mmio_regions(struct domain *d, paddr_t start_gaddr,
paddr_t end_gaddr, paddr_t maddr);
/* Map MMIO regions in the p2m: start_gfn and end_gfn is the range in the guest
* physical address space to map, starting from the machine frame number mfn. */
int map_mmio_regions(struct domain *d,
unsigned long start_gfn,
unsigned long end_gfn,
unsigned long mfn);
int guest_physmap_add_entry(struct domain *d,
unsigned long gfn,
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