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x86emul: use msr definitions in msr-index.h
Change the names used in code according to numeric values. Remove the now unused macros in x86_emualte.c and fix indentation. This in turns requires including msr-index.h and removing duplicates in userspace x86_emulate.c in userspace harness program. No functional change. Signed-off-by: Wei Liu <wei.liu2@citrix.com> Reviewed-by: Jan Beulich <jbeulich@suse.com>
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@@ -11,7 +11,7 @@ endif
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x86_emulate/x86_emulate.c x86_emulate/x86_emulate.h:
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[ -L x86_emulate ] || ln -sf $(XEN_ROOT)/xen/arch/x86/x86_emulate .
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asm/x86-vendors.h asm/x86-defns.h:
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asm/x86-vendors.h asm/x86-defns.h asm/msr-index.h:
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[ -L asm ] || ln -sf $(XEN_ROOT)/xen/include/asm-x86 asm
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x86_emulate.c x86_emulate.h: %:
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@@ -19,7 +19,7 @@ x86_emulate.c x86_emulate.h: %:
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CFLAGS += $(CFLAGS_xeninclude) -D__XEN_TOOLS__ -I.
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x86.h := asm/x86-vendors.h asm/x86-defns.h
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x86.h := asm/x86-vendors.h asm/x86-defns.h asm/msr-index.h
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x86_emulate.h := x86_emulate.h x86_emulate/x86_emulate.h $(x86.h)
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x86_emulate.o: x86_emulate.c x86_emulate/x86_emulate.c $(x86_emulate.h)
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@@ -43,12 +43,12 @@ install:
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x86_emulate/x86_emulate.c x86_emulate/x86_emulate.h:
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[ -L x86_emulate ] || ln -sf $(XEN_ROOT)/xen/arch/x86/x86_emulate .
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asm/x86-vendors.h asm/x86-defns.h:
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asm/x86-vendors.h asm/x86-defns.h asm/msr-index.h:
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[ -L asm ] || ln -sf $(XEN_ROOT)/xen/include/asm-x86 asm
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HOSTCFLAGS += $(CFLAGS_xeninclude) -I.
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x86.h := asm/x86-vendors.h asm/x86-defns.h
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x86.h := asm/x86-vendors.h asm/x86-defns.h asm/msr-index.h
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x86_emulate.h := x86_emulate.h x86_emulate/x86_emulate.h $(x86.h)
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x86_emulate.o: x86_emulate.c x86_emulate/x86_emulate.c $(x86_emulate.h)
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@@ -2,9 +2,6 @@
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#include <sys/mman.h>
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#define EFER_SCE (1 << 0)
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#define EFER_LMA (1 << 10)
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#define cpu_has_amd_erratum(nr) 0
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#define mark_regs_dirty(r) ((void)(r))
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#define cpu_has_mpx false
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@@ -6,6 +6,7 @@
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#include <string.h>
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#include <xen/xen.h>
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#include <asm/msr-index.h>
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#include <asm/x86-defns.h>
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#include <asm/x86-vendors.h>
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@@ -415,23 +415,6 @@ typedef union {
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# define ASM_FLAG_OUT(yes, no) no
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#endif
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/* MSRs. */
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#define MSR_TSC 0x00000010
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#define MSR_SYSENTER_CS 0x00000174
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#define MSR_SYSENTER_ESP 0x00000175
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#define MSR_SYSENTER_EIP 0x00000176
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#define MSR_DEBUGCTL 0x000001d9
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#define DEBUGCTL_BTF (1 << 1)
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#define MSR_BNDCFGS 0x00000d90
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#define BNDCFG_ENABLE (1 << 0)
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#define BNDCFG_PRESERVE (1 << 1)
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#define MSR_EFER 0xc0000080
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#define MSR_STAR 0xc0000081
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#define MSR_LSTAR 0xc0000082
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#define MSR_CSTAR 0xc0000083
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#define MSR_FMASK 0xc0000084
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#define MSR_TSC_AUX 0xc0000103
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/* Control register flags. */
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#define CR0_PE (1<<0)
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#define CR0_MP (1<<1)
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@@ -1731,8 +1714,8 @@ static bool is_branch_step(struct x86_emulate_ctxt *ctxt,
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uint64_t debugctl;
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return ops->read_msr &&
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ops->read_msr(MSR_DEBUGCTL, &debugctl, ctxt) == X86EMUL_OKAY &&
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(debugctl & DEBUGCTL_BTF);
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ops->read_msr(MSR_IA32_DEBUGCTLMSR, &debugctl, ctxt) == X86EMUL_OKAY &&
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(debugctl & IA32_DEBUGCTLMSR_BTF);
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}
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static bool umip_active(struct x86_emulate_ctxt *ctxt,
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@@ -1894,9 +1877,9 @@ static void adjust_bnd(struct x86_emulate_ctxt *ctxt,
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if ( !mode_ring0() )
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bndcfg = read_bndcfgu();
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else if ( !ops->read_msr ||
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ops->read_msr(MSR_BNDCFGS, &bndcfg, ctxt) != X86EMUL_OKAY )
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ops->read_msr(MSR_IA32_BNDCFGS, &bndcfg, ctxt) != X86EMUL_OKAY )
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return;
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if ( (bndcfg & BNDCFG_ENABLE) && !(bndcfg & BNDCFG_PRESERVE) )
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if ( (bndcfg & IA32_BNDCFGS_ENABLE) && !(bndcfg & IA32_BNDCFGS_PRESERVE) )
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{
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/*
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* Using BNDMK or any other MPX instruction here is pointless, as
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@@ -4983,7 +4966,7 @@ x86_emulate(
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goto done;
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_regs.rip = msr_content;
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if ( (rc = ops->read_msr(MSR_FMASK, &msr_content, ctxt)) != 0 )
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if ( (rc = ops->read_msr(MSR_SYSCALL_MASK, &msr_content, ctxt)) != 0 )
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goto done;
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_regs._eflags &= ~(msr_content | X86_EFLAGS_RF);
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}
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@@ -5009,7 +4992,7 @@ x86_emulate(
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* As the #DB is raised after the CPL change and before the OS can
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* switch stack, it is a large risk for privilege escalation.
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*
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* 64bit kernels should mask EFLAGS.TF in MSR_FMASK to avoid any
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* 64bit kernels should mask EFLAGS.TF in MSR_SYSCALL_MASK to avoid any
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* vulnerability. Running the #DB handler on an IST stack is also a
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* mitigation.
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*
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@@ -5207,7 +5190,7 @@ x86_emulate(
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generate_exception_if(cr4 & CR4_TSD, EXC_GP, 0);
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}
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fail_if(ops->read_msr == NULL);
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if ( (rc = ops->read_msr(MSR_TSC, &val, ctxt)) != 0 )
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if ( (rc = ops->read_msr(MSR_IA32_TSC, &val, ctxt)) != 0 )
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goto done;
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_regs.r(dx) = val >> 32;
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_regs.r(ax) = (uint32_t)val;
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@@ -5240,7 +5223,8 @@ x86_emulate(
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generate_exception_if(!in_protmode(ctxt, ops), EXC_GP, 0);
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fail_if(ops->read_msr == NULL);
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if ( (rc = ops->read_msr(MSR_SYSENTER_CS, &msr_content, ctxt)) != 0 )
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if ( (rc = ops->read_msr(MSR_IA32_SYSENTER_CS, &msr_content, ctxt))
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!= 0 )
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goto done;
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generate_exception_if(!(msr_content & 0xfffc), EXC_GP, 0);
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@@ -5266,11 +5250,13 @@ x86_emulate(
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(rc = ops->write_segment(x86_seg_ss, &sreg, ctxt)) != 0 )
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goto done;
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if ( (rc = ops->read_msr(MSR_SYSENTER_EIP, &msr_content, ctxt)) != 0 )
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if ( (rc = ops->read_msr(MSR_IA32_SYSENTER_EIP, &msr_content, ctxt))
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!= 0 )
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goto done;
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_regs.r(ip) = lm ? msr_content : (uint32_t)msr_content;
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if ( (rc = ops->read_msr(MSR_SYSENTER_ESP, &msr_content, ctxt)) != 0 )
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if ( (rc = ops->read_msr(MSR_IA32_SYSENTER_ESP, &msr_content, ctxt))
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!= 0 )
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goto done;
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_regs.r(sp) = lm ? msr_content : (uint32_t)msr_content;
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@@ -5287,7 +5273,8 @@ x86_emulate(
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generate_exception_if(!in_protmode(ctxt, ops), EXC_GP, 0);
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fail_if(ops->read_msr == NULL);
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if ( (rc = ops->read_msr(MSR_SYSENTER_CS, &msr_content, ctxt)) != 0 )
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if ( (rc = ops->read_msr(MSR_IA32_SYSENTER_CS, &msr_content, ctxt))
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!= 0 )
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goto done;
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generate_exception_if(!(msr_content & 0xfffc), EXC_GP, 0);
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