diff --git a/tools/libxl/libxl_cpuid.c b/tools/libxl/libxl_cpuid.c index 24591e2461..8292654c86 100644 --- a/tools/libxl/libxl_cpuid.c +++ b/tools/libxl/libxl_cpuid.c @@ -158,6 +158,8 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str) {"de", 0x00000001, NA, CPUID_REG_EDX, 2, 1}, {"vme", 0x00000001, NA, CPUID_REG_EDX, 1, 1}, {"fpu", 0x00000001, NA, CPUID_REG_EDX, 0, 1}, + {"ibrsb", 0x00000007, 0, CPUID_REG_EDX, 26, 1}, + {"stibp", 0x00000007, 0, CPUID_REG_EDX, 27, 1}, {"topoext", 0x80000001, NA, CPUID_REG_ECX, 22, 1}, {"tbm", 0x80000001, NA, CPUID_REG_ECX, 21, 1}, {"nodeid", 0x80000001, NA, CPUID_REG_ECX, 19, 1}, @@ -187,6 +189,7 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str) {"nx", 0x80000001, NA, CPUID_REG_EDX, 20, 1}, {"syscall", 0x80000001, NA, CPUID_REG_EDX, 11, 1}, {"procpkg", 0x00000004, 0, CPUID_REG_EAX, 26, 6}, + {"ibpb", 0x80000008, NA, CPUID_REG_EBX, 12, 1}, {"apicidsize", 0x80000008, NA, CPUID_REG_ECX, 12, 4}, {"nc", 0x80000008, NA, CPUID_REG_ECX, 0, 8}, {"svm_npt", 0x8000000a, NA, CPUID_REG_EDX, 0, 1}, diff --git a/tools/misc/xen-cpuid.c b/tools/misc/xen-cpuid.c index 106be0f8a3..0bb2bca975 100644 --- a/tools/misc/xen-cpuid.c +++ b/tools/misc/xen-cpuid.c @@ -144,7 +144,11 @@ static const char *str_e8b[32] = { [ 0] = "clzero", - [1 ... 31] = "REZ", + [1 ... 11] = "REZ", + + [12] = "ibpb", + + [13 ... 31] = "REZ", }; static const char *str_7d0[32] = @@ -153,7 +157,11 @@ static const char *str_7d0[32] = [ 2] = "avx512_4vnniw", [ 3] = "avx512_4fmaps", - [4 ... 31] = "REZ", + [4 ... 25] = "REZ", + + [26] = "ibrsb", [27] = "stibp", + + [28 ... 31] = "REZ", }; static struct { diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c index d601c028d8..89e7287e43 100644 --- a/xen/arch/x86/spec_ctrl.c +++ b/xen/arch/x86/spec_ctrl.c @@ -67,8 +67,25 @@ custom_param("bti", parse_bti); static void __init print_details(enum ind_thunk thunk) { + unsigned int _7d0 = 0, e8b = 0, tmp; + + /* Collect diagnostics about available mitigations. */ + if ( boot_cpu_data.cpuid_level >= 7 ) + cpuid_count(7, 0, &tmp, &tmp, &tmp, &_7d0); + if ( boot_cpu_data.extended_cpuid_level >= 0x80000008 ) + cpuid(0x80000008, &tmp, &e8b, &tmp, &tmp); + printk(XENLOG_DEBUG "Speculative mitigation facilities:\n"); + /* Hardware features which pertain to speculative mitigations. */ + if ( (_7d0 & (cpufeat_mask(X86_FEATURE_IBRSB) | + cpufeat_mask(X86_FEATURE_STIBP))) || + (e8b & cpufeat_mask(X86_FEATURE_IBPB)) ) + printk(XENLOG_DEBUG " Hardware features:%s%s%s\n", + (_7d0 & cpufeat_mask(X86_FEATURE_IBRSB)) ? " IBRS/IBPB" : "", + (_7d0 & cpufeat_mask(X86_FEATURE_STIBP)) ? " STIBP" : "", + (e8b & cpufeat_mask(X86_FEATURE_IBPB)) ? " IBPB" : ""); + /* Compiled-in support which pertains to BTI mitigations. */ if ( IS_ENABLED(CONFIG_INDIRECT_THUNK) ) printk(XENLOG_DEBUG " Compiled-in support: INDIRECT_THUNK\n"); diff --git a/xen/include/asm-x86/cpufeatures.h b/xen/include/asm-x86/cpufeatures.h index fb2ede22e1..71abf4342b 100644 --- a/xen/include/asm-x86/cpufeatures.h +++ b/xen/include/asm-x86/cpufeatures.h @@ -27,3 +27,6 @@ XEN_CPUFEATURE(MSR_MISC_FEATURES, (FSCAPINTS+0)*32+13) /* MISC_FEATURES_ENABLES XEN_CPUFEATURE(LFENCE_DISPATCH, (FSCAPINTS+0)*32+14) /* lfence set as Dispatch Serialising */ XEN_CPUFEATURE(IND_THUNK_LFENCE,(FSCAPINTS+0)*32+15) /* Use IND_THUNK_LFENCE */ XEN_CPUFEATURE(IND_THUNK_JMP, (FSCAPINTS+0)*32+16) /* Use IND_THUNK_JMP */ +XEN_CPUFEATURE(XEN_IBPB, (FSCAPINTS+0)*32+17) /* IBRSB || IBPB */ +XEN_CPUFEATURE(XEN_IBRS_SET, (FSCAPINTS+0)*32+18) /* IBRSB && IRBS set in Xen */ +XEN_CPUFEATURE(XEN_IBRS_CLEAR, (FSCAPINTS+0)*32+19) /* IBRSB && IBRS clear in Xen */ diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h index be64350040..bc17bb69fa 100644 --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -31,6 +31,14 @@ #define EFER_LMSLE (1<<_EFER_LMSLE) #define EFER_FFXSE (1<<_EFER_FFXSE) +/* Speculation Controls. */ +#define MSR_SPEC_CTRL 0x00000048 +#define SPEC_CTRL_IBRS (_AC(1, ULL) << 0) +#define SPEC_CTRL_STIBP (_AC(1, ULL) << 1) + +#define MSR_PRED_CMD 0x00000049 +#define PRED_CMD_IBPB (_AC(1, ULL) << 0) + /* Intel MSRs. Some also available on other CPUs */ #define MSR_IA32_PERFCTR0 0x000000c1 #define MSR_IA32_A_PERFCTR0 0x000004c1 diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h index 97dd3534c5..9ff91874dd 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -236,10 +236,13 @@ XEN_CPUFEATURE(EFRO, 7*32+10) /* APERF/MPERF Read Only interface */ /* AMD-defined CPU features, CPUID level 0x80000008.ebx, word 8 */ XEN_CPUFEATURE(CLZERO, 8*32+ 0) /*A CLZERO instruction */ +XEN_CPUFEATURE(IBPB, 8*32+12) /* IBPB support only (no IBRS, used by AMD) */ /* Intel-defined CPU features, CPUID level 0x00000007:0.edx, word 9 */ -XEN_CPUFEATURE(AVX512_4VNNIW, 9*32+ 2) /*A AVX512 Neural Network Instructions */ -XEN_CPUFEATURE(AVX512_4FMAPS, 9*32+ 3) /*A AVX512 Multiply Accumulation Single Precision */ +XEN_CPUFEATURE(AVX512_4VNNIW, 9*32+ 2) /*A AVX512 Neural Network Instructions */ +XEN_CPUFEATURE(AVX512_4FMAPS, 9*32+ 3) /*A AVX512 Multiply Accumulation Single Precision */ +XEN_CPUFEATURE(IBRSB, 9*32+26) /* IBRS and IBPB support (used by Intel) */ +XEN_CPUFEATURE(STIBP, 9*32+27) /* STIBP */ #endif /* XEN_CPUFEATURE */ diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py index 9ec4486f2b..613b909c3d 100755 --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -256,6 +256,11 @@ def crunch_numbers(state): AVX512F: [AVX512DQ, AVX512IFMA, AVX512PF, AVX512ER, AVX512CD, AVX512BW, AVX512VL, AVX512VBMI, AVX512_4VNNIW, AVX512_4FMAPS, AVX512_VPOPCNTDQ], + + # Single Thread Indirect Branch Predictors enumerates a new bit in the + # MSR enumerated by Indirect Branch Restricted Speculation/Indirect + # Branch Prediction Barrier enumeration. + IBRSB: [STIBP], } deep_features = tuple(sorted(deps.keys()))