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pl011: set baud and clock_hz to the right defaults for Versatile Express
Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Acked-by: Tim Deegan <tim@xen.org> Committed-by: Ian Campbell <ian.campbell@citrix.com>
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286e93ad79
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1 file changed
+2
-2
@@ -241,8 +241,8 @@ void __init pl011_init(int index, unsigned long register_base_address)
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uart = &pl011_com[index];
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uart->clock_hz = 7372800;
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uart->baud = 115200;
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uart->clock_hz = 0x16e3600;
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uart->baud = 38400;
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uart->data_bits = 8;
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uart->parity = PARITY_NONE;
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uart->stop_bits = 1;
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