pl011: set baud and clock_hz to the right defaults for Versatile Express

Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Acked-by: Tim Deegan <tim@xen.org>
Committed-by: Ian Campbell <ian.campbell@citrix.com>
This commit is contained in:
Stefano Stabellini committed 2012-11-15 10:25:27 +00:00
1 parent 286e93ad79
commit 60ff944448
1 file changed
+2 -2
+2 -2
View File
@@ -241,8 +241,8 @@ void __init pl011_init(int index, unsigned long register_base_address)
uart = &pl011_com[index];
uart->clock_hz = 7372800;
uart->baud = 115200;
uart->clock_hz = 0x16e3600;
uart->baud = 38400;
uart->data_bits = 8;
uart->parity = PARITY_NONE;
uart->stop_bits = 1;
Reference in new issue
Block a user
Blocking a user prevents them from interacting with repositories, such as opening or commenting on pull requests or issues. Learn more about blocking a user.