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x86/S3: Save and restore Shadow Stack configuration
See code for details. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Reviewed-by: Jan Beulich <jbeulich@suse.com>
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@@ -1,3 +1,7 @@
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#include <asm/msr-index.h>
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#include <asm/page.h>
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#include <asm/processor.h>
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.file __FILE__
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.text
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.code64
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@@ -15,6 +19,12 @@ ENTRY(do_suspend_lowlevel)
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mov %cr0, %rax
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mov %rax, saved_cr0(%rip)
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#ifdef CONFIG_XEN_SHSTK
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mov $1, %eax
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rdsspq %rax
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mov %rax, saved_ssp(%rip)
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#endif
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/* enter sleep state physically */
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mov $3, %edi
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call acpi_enter_sleep_state
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@@ -48,6 +58,51 @@ ENTRY(s3_resume)
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pushq %rax
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lretq
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1:
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#ifdef CONFIG_XEN_SHSTK
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/*
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* Restoring SSP is a little complicated, because we are intercepting
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* an in-use shadow stack. Write a temporary token under the stack,
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* so SETSSBSY will successfully load a value useful for us, then
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* reset MSR_PL0_SSP to its usual value and pop the temporary token.
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*/
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mov saved_rsp(%rip), %rdi
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cmpq $1, %rdi
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je .L_shstk_done
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/* Set up MSR_S_CET. */
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mov $MSR_S_CET, %ecx
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xor %edx, %edx
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mov $CET_SHSTK_EN | CET_WRSS_EN, %eax
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wrmsr
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/* Construct the temporary supervisor token under SSP. */
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sub $8, %rdi
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/* Load it into MSR_PL0_SSP. */
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mov $MSR_PL0_SSP, %ecx
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mov %rdi, %rdx
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shr $32, %rdx
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mov %edi, %eax
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wrmsr
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/* Enable CET. MSR_INTERRUPT_SSP_TABLE is set up later in load_system_tables(). */
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mov $XEN_MINIMAL_CR4 | X86_CR4_CET, %ebx
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mov %rbx, %cr4
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/* Write the temporary token onto the shadow stack, and activate it. */
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wrssq %rdi, (%rdi)
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setssbsy
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/* Reset MSR_PL0_SSP back to its normal value. */
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and $~(STACK_SIZE - 1), %eax
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or $(PRIMARY_SHSTK_SLOT + 1) * PAGE_SIZE - 8, %eax
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wrmsr
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/* Pop the temporary token off the stack. */
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mov $2, %eax
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incsspd %eax
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.L_shstk_done:
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#endif
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call load_system_tables
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@@ -65,6 +120,9 @@ ENTRY(s3_resume)
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saved_rsp: .quad 0
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saved_cr0: .quad 0
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#ifdef CONFIG_XEN_SHSTK
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saved_ssp: .quad 0
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#endif
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GLOBAL(saved_magic)
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.long 0x9abcdef0
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@@ -68,6 +68,9 @@
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#define MSR_U_CET 0x000006a0
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#define MSR_S_CET 0x000006a2
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#define CET_SHSTK_EN (_AC(1, ULL) << 0)
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#define CET_WRSS_EN (_AC(1, ULL) << 1)
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#define MSR_PL0_SSP 0x000006a4
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#define MSR_PL1_SSP 0x000006a5
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#define MSR_PL2_SSP 0x000006a6
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@@ -73,6 +73,7 @@
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#define X86_CR4_SMEP 0x00100000 /* enable SMEP */
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#define X86_CR4_SMAP 0x00200000 /* enable SMAP */
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#define X86_CR4_PKE 0x00400000 /* enable PKE */
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#define X86_CR4_CET 0x00800000 /* Control-flow Enforcement Technology */
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/*
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* XSTATE component flags in XCR0
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