x86/pv: Options to disable and/or compile out 32bit PV support

This is the start of some performance and security-hardening improvements,
based on the fact that 32bit PV guests are few and far between these days.

Ring1 is full of architectural corner cases, such as counting as supervisor
from a paging point of view.  This accounts for a substantial performance hit
on processors from the last 8 years (adjusting SMEP/SMAP on every privilege
transition), and the gap is only going to get bigger with new hardware
features.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Wei Liu <wl@xen.org>
Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
Acked-by: Jan Beulich <jbeulich@suse.com>
This commit is contained in:
Andrew Cooper committed 2020-04-29 21:13:00 +01:00
1 parent 4304ff420e
commit 68d757df8d
6 files changed
+83 -3

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+11 -1
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@@ -1694,7 +1694,17 @@ The following resources are available:
CDP, one COS will corespond two CBMs other than one with CAT, due to the
sum of CBMs is fixed, that means actual `cos_max` in use will automatically
reduce to half when CDP is enabled.
### pv
= List of [ 32=<bool> ]
Applicability: x86
Controls for aspects of PV guest support.
* The `32` boolean controls whether 32bit PV guests can be created. It
defaults to `true`, and is ignored when `CONFIG_PV32` is compiled out.
### pv-linear-pt (x86)
> `= <boolean>`
+16
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@@ -49,6 +49,22 @@ config PV
If unsure, say Y.
config PV32
bool "Support for 32bit PV guests"
depends on PV
default y
---help---
The 32bit PV ABI uses Ring1, an area of the x86 architecture which
was deprecated and mostly removed in the AMD64 spec. As a result,
it occasionally conflicts with newer x86 hardware features, causing
overheads for Xen to maintain backwards compatibility.
People may wish to disable 32bit PV guests for attack surface
reduction, or performance reasons. Backwards compatibility can be
provided via the PV Shim mechanism.
If unsure, say Y.
config PV_LINEAR_PT
bool "Support for PV linear pagetables"
depends on PV
+34
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@@ -16,6 +16,38 @@
#include <asm/pv/domain.h>
#include <asm/shadow.h>
#ifdef CONFIG_PV32
int8_t __read_mostly opt_pv32 = -1;
#endif
static __init int parse_pv(const char *s)
{
const char *ss;
int val, rc = 0;
do {
ss = strchr(s, ',');
if ( !ss )
ss = strchr(s, '\0');
if ( (val = parse_boolean("32", s, ss)) >= 0 )
{
#ifdef CONFIG_PV32
opt_pv32 = val;
#else
no_config_param("PV32", "pv", s, ss);
#endif
}
else
rc = -EINVAL;
s = ss + 1;
} while ( *ss );
return rc;
}
custom_param("pv", parse_pv);
static __read_mostly enum {
PCID_OFF,
PCID_ALL,
@@ -174,6 +206,8 @@ int switch_compat(struct domain *d)
BUILD_BUG_ON(offsetof(struct shared_info, vcpu_info) != 0);
if ( !opt_pv32 )
return -EOPNOTSUPP;
if ( is_hvm_domain(d) || domain_tot_pages(d) != 0 )
return -EACCES;
if ( is_pv_32bit_domain(d) )
+7 -2
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@@ -53,6 +53,7 @@
#include <asm/spec_ctrl.h>
#include <asm/guest.h>
#include <asm/microcode.h>
#include <asm/pv/domain.h>
/* opt_nosmp: If true, secondary processors are ignored. */
static bool __initdata opt_nosmp;
@@ -1870,8 +1871,12 @@ void arch_get_xen_caps(xen_capabilities_info_t *info)
{
snprintf(s, sizeof(s), "xen-%d.%d-x86_64 ", major, minor);
safe_strcat(*info, s);
snprintf(s, sizeof(s), "xen-%d.%d-x86_32p ", major, minor);
safe_strcat(*info, s);
if ( opt_pv32 )
{
snprintf(s, sizeof(s), "xen-%d.%d-x86_32p ", major, minor);
safe_strcat(*info, s);
}
}
if ( hvm_enabled )
{
+6
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@@ -23,6 +23,12 @@
#include <xen/sched.h>
#ifdef CONFIG_PV32
extern int8_t opt_pv32;
#else
# define opt_pv32 false
#endif
/*
* PCID values for the address spaces of 64-bit pv domains:
*
+9
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@@ -127,4 +127,13 @@ extern const struct kernel_param __param_start[], __param_end[];
string_param(_name, _var); \
string_runtime_only_param(_name, _var)
static inline void no_config_param(const char *cfg, const char *param,
const char *s, const char *e)
{
int len = e ? ({ ASSERT(e >= s); e - s; }) : strlen(s);
printk(XENLOG_INFO "CONFIG_%s disabled - ignoring '%s=%*s' setting\n",
cfg, param, len, s);
}
#endif /* _XEN_PARAM_H */
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