diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index 2317546999..4ff0b54629 100644
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -661,6 +661,18 @@ static void init_amd(struct cpuinfo_x86 *c)
 				       smp_processor_id());
 			wrmsrl(MSR_AMD64_LS_CFG, value | (1 << 15));
 		}
+	} else if (c->x86 == 0x12) {
+		rdmsrl(MSR_AMD64_DE_CFG, value);
+		if (!(value & (1U << 31))) {
+			static bool warned;
+
+			if (c == &boot_cpu_data || opt_cpu_info ||
+			    !test_and_set_bool(warned))
+				printk(KERN_WARNING
+				       "CPU%u: Applying workaround for erratum 665\n",
+				       smp_processor_id());
+			wrmsrl(MSR_AMD64_DE_CFG, value | (1U << 31));
+		}
 	}
 
 	/* AMD CPUs do not support SYSENTER outside of legacy mode. */
diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index deb82a771c..98dbff1337 100644
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -199,10 +199,11 @@
 
 /* AMD64 MSRs */
 #define MSR_AMD64_NB_CFG		0xc001001f
+#define AMD64_NB_CFG_CF8_EXT_ENABLE_BIT	46
 #define MSR_AMD64_LS_CFG		0xc0011020
 #define MSR_AMD64_IC_CFG		0xc0011021
 #define MSR_AMD64_DC_CFG		0xc0011022
-#define AMD64_NB_CFG_CF8_EXT_ENABLE_BIT	46
+#define MSR_AMD64_DE_CFG		0xc0011029
 
 #define MSR_AMD64_DR0_ADDRESS_MASK	0xc0011027
 #define MSR_AMD64_DR1_ADDRESS_MASK	0xc0011019