diff --git a/tools/firmware/hvmloader/config.h b/tools/firmware/hvmloader/config.h index c82adf6dc5..cd716bf392 100644 --- a/tools/firmware/hvmloader/config.h +++ b/tools/firmware/hvmloader/config.h @@ -44,7 +44,6 @@ extern struct bios_config ovmf_config; #define PAGE_SHIFT 12 #define PAGE_SIZE (1ul << PAGE_SHIFT) -extern uint32_t ioapic_base_address; extern uint8_t ioapic_version; #define IOAPIC_ID 0x01 diff --git a/tools/firmware/hvmloader/hvmloader.c b/tools/firmware/hvmloader/hvmloader.c index c58841e5b5..f8af88fabf 100644 --- a/tools/firmware/hvmloader/hvmloader.c +++ b/tools/firmware/hvmloader/hvmloader.c @@ -113,7 +113,6 @@ asm ( unsigned long scratch_start = SCRATCH_PHYSICAL_ADDRESS; -uint32_t ioapic_base_address = 0xfec00000; uint8_t ioapic_version; bool acpi_enabled; diff --git a/tools/firmware/hvmloader/mp_tables.c b/tools/firmware/hvmloader/mp_tables.c index d207ecbf00..77d3010406 100644 --- a/tools/firmware/hvmloader/mp_tables.c +++ b/tools/firmware/hvmloader/mp_tables.c @@ -229,7 +229,7 @@ static void fill_mp_ioapic_entry(struct mp_ioapic_entry *mpie) mpie->ioapic_id = IOAPIC_ID; mpie->ioapic_version = ioapic_version; mpie->ioapic_flags = 1; /* enabled */ - mpie->ioapic_addr = ioapic_base_address; + mpie->ioapic_addr = IOAPIC_BASE_ADDRESS; } diff --git a/tools/firmware/hvmloader/util.c b/tools/firmware/hvmloader/util.c index e82047d993..c34f077b38 100644 --- a/tools/firmware/hvmloader/util.c +++ b/tools/firmware/hvmloader/util.c @@ -42,60 +42,6 @@ bool check_overlap(uint64_t start, uint64_t size, (start < reserved_start + reserved_size); } -void wrmsr(uint32_t idx, uint64_t v) -{ - asm volatile ( - "wrmsr" - : : "c" (idx), "a" ((uint32_t)v), "d" ((uint32_t)(v>>32)) ); -} - -uint64_t rdmsr(uint32_t idx) -{ - uint32_t lo, hi; - - asm volatile ( - "rdmsr" - : "=a" (lo), "=d" (hi) : "c" (idx) ); - - return (lo | ((uint64_t)hi << 32)); -} - -void outb(uint16_t addr, uint8_t val) -{ - asm volatile ( "outb %%al, %%dx" : : "d" (addr), "a" (val) ); -} - -void outw(uint16_t addr, uint16_t val) -{ - asm volatile ( "outw %%ax, %%dx" : : "d" (addr), "a" (val) ); -} - -void outl(uint16_t addr, uint32_t val) -{ - asm volatile ( "outl %%eax, %%dx" : : "d" (addr), "a" (val) ); -} - -uint8_t inb(uint16_t addr) -{ - uint8_t val; - asm volatile ( "inb %%dx,%%al" : "=a" (val) : "d" (addr) ); - return val; -} - -uint16_t inw(uint16_t addr) -{ - uint16_t val; - asm volatile ( "inw %%dx,%%ax" : "=a" (val) : "d" (addr) ); - return val; -} - -uint32_t inl(uint16_t addr) -{ - uint32_t val; - asm volatile ( "inl %%dx,%%eax" : "=a" (val) : "d" (addr) ); - return val; -} - uint8_t cmos_inb(uint8_t idx) { outb(0x70, idx); @@ -493,28 +439,6 @@ void *scratch_alloc(uint32_t size, uint32_t align) return (void *)(unsigned long)s; } -uint32_t ioapic_read(uint32_t reg) -{ - *(volatile uint32_t *)(ioapic_base_address + 0x00) = reg; - return *(volatile uint32_t *)(ioapic_base_address + 0x10); -} - -void ioapic_write(uint32_t reg, uint32_t val) -{ - *(volatile uint32_t *)(ioapic_base_address + 0x00) = reg; - *(volatile uint32_t *)(ioapic_base_address + 0x10) = val; -} - -uint32_t lapic_read(uint32_t reg) -{ - return *(volatile uint32_t *)(LAPIC_BASE_ADDRESS + reg); -} - -void lapic_write(uint32_t reg, uint32_t val) -{ - *(volatile uint32_t *)(LAPIC_BASE_ADDRESS + reg) = val; -} - #define PCI_CONF1_ADDRESS(bus, devfn, reg) \ (0x80000000 | (bus << 16) | (devfn << 8) | (reg & ~3)) @@ -945,7 +869,7 @@ void hvmloader_acpi_build_tables(struct acpi_config *config, config->lapic_base_address = LAPIC_BASE_ADDRESS; config->lapic_id = acpi_lapic_id; - config->ioapic_base_address = ioapic_base_address; + config->ioapic_base_address = IOAPIC_BASE_ADDRESS; config->ioapic_id = IOAPIC_ID; config->pci_isa_irq_mask = PCI_ISA_IRQ_MASK; diff --git a/tools/firmware/hvmloader/util.h b/tools/firmware/hvmloader/util.h index 14078bde1e..deb823a892 100644 --- a/tools/firmware/hvmloader/util.h +++ b/tools/firmware/hvmloader/util.h @@ -7,6 +7,7 @@ #include #include #include +#include "config.h" #include "e820.h" #include @@ -54,28 +55,113 @@ static inline int test_and_clear_bit(int nr, volatile void *addr) } /* MSR access */ -void wrmsr(uint32_t idx, uint64_t v); -uint64_t rdmsr(uint32_t idx); +static inline void wrmsr(uint32_t idx, uint64_t v) +{ + asm volatile ( "wrmsr" :: "c" (idx), "A" (v) ); +} + +static inline uint64_t rdmsr(uint32_t idx) +{ + uint64_t res; + + asm volatile ( "rdmsr" : "=A" (res) : "c" (idx) ); + + return res; +} /* I/O output */ -void outb(uint16_t addr, uint8_t val); -void outw(uint16_t addr, uint16_t val); -void outl(uint16_t addr, uint32_t val); +static inline void outb(uint16_t port, uint8_t val) +{ + asm volatile ( "outb %[val], %[port]" + : + : [port] "Nd" (port), + [val] "a" (val) + : "memory" ); +} + +static inline void outw(uint16_t port, uint16_t val) +{ + asm volatile ( "outw %[val], %[port]" + : + : [port] "Nd" (port), + [val] "a" (val) + : "memory" ); +} + +static inline void outl(uint16_t port, uint32_t val) +{ + asm volatile ( "outl %[val], %[port]" + : + : [port] "Nd" (port), + [val] "a" (val) + : "memory" ); +} /* I/O input */ -uint8_t inb(uint16_t addr); -uint16_t inw(uint16_t addr); -uint32_t inl(uint16_t addr); +static inline uint8_t inb(uint16_t port) +{ + uint8_t val; + + asm volatile ( "inb %[port], %[val]" + : [val] "=a" (val) + : [port] "Nd" (port) + : "memory" ); + + return val; +} + +static inline uint16_t inw(uint16_t port) +{ + uint16_t val; + + asm volatile ( "inw %[port], %[val]" + : [val] "=a" (val) + : [port] "Nd" (port) + : "memory" ); + + return val; +} + +static inline uint32_t inl(uint16_t port) +{ + uint32_t val; + + asm volatile ( "inl %[port], %[val]" + : [val] "=a" (val) + : [port] "Nd" (port) + : "memory" ); + + return val; +} /* CMOS access */ uint8_t cmos_inb(uint8_t idx); void cmos_outb(uint8_t idx, uint8_t val); /* APIC access */ -uint32_t ioapic_read(uint32_t reg); -void ioapic_write(uint32_t reg, uint32_t val); -uint32_t lapic_read(uint32_t reg); -void lapic_write(uint32_t reg, uint32_t val); +#define IOAPIC_BASE_ADDRESS 0xfec00000 +static inline uint32_t ioapic_read(uint32_t reg) +{ + *(volatile uint32_t *)(IOAPIC_BASE_ADDRESS + 0x00) = reg; + return *(volatile uint32_t *)(IOAPIC_BASE_ADDRESS + 0x10); +} + +static inline void ioapic_write(uint32_t reg, uint32_t val) +{ + *(volatile uint32_t *)(IOAPIC_BASE_ADDRESS + 0x00) = reg; + *(volatile uint32_t *)(IOAPIC_BASE_ADDRESS + 0x10) = val; +} + +#define LAPIC_BASE_ADDRESS 0xfee00000 +static inline uint32_t lapic_read(uint32_t reg) +{ + return *(volatile uint32_t *)(LAPIC_BASE_ADDRESS + reg); +} + +static inline void lapic_write(uint32_t reg, uint32_t val) +{ + *(volatile uint32_t *)(LAPIC_BASE_ADDRESS + reg) = val; +} /* PCI access */ uint32_t pci_read(uint32_t devfn, uint32_t reg, uint32_t len);