diff --git a/xen/arch/arm/include/asm/processor.h b/xen/arch/arm/include/asm/processor.h
index 509040a1cd..8ee8f88fb4 100644
--- a/xen/arch/arm/include/asm/processor.h
+++ b/xen/arch/arm/include/asm/processor.h
@@ -507,7 +507,6 @@ extern register_t __cpu_logical_map[];
 /* .... If F == 1 */
 #define PAR_FSC_SHIFT   (1)
 #define PAR_FSC_MASK    (_AC(0x3f,U)<<PAR_FSC_SHIFT)
-#define PAR_STAGE21     (_AC(1,U)<<8)     /* Stage 2 Fault During Stage 1 Walk */
 #define PAR_STAGE2      (_AC(1,U)<<9)     /* Stage 2 Fault */
 
 /* If F == 0 */
diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index 344aa21b98..625d229396 100644
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/traps.c
@@ -379,16 +379,17 @@ void panic_PAR(uint64_t par)
 {
     const char *msg;
     int level = -1;
-    int stage = par & PAR_STAGE2 ? 2 : 1;
-    int second_in_first = !!(par & PAR_STAGE21);
 
-    msg = decode_fsc( (par&PAR_FSC_MASK) >> PAR_FSC_SHIFT, &level);
+    /*
+     * The only caller translates using "at s1e2r" (arm64) or ATS1HR
+     * (arm32), i.e. an EL2 stage 1 only translation.
+     */
+    ASSERT(!(par & PAR_STAGE2));
 
-    printk("PAR: %016"PRIx64": %s stage %d%s%s\n",
-           par, msg,
-           stage,
-           second_in_first ? " during second stage lookup" : "",
-           fsc_level_str(level));
+    msg = decode_fsc((par & PAR_FSC_MASK) >> PAR_FSC_SHIFT, &level);
+
+    printk("PAR: %016"PRIx64": %s stage 1%s\n",
+           par, msg, fsc_level_str(level));
 
     panic("Error during Hypervisor-to-physical address translation\n");
 }