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x86emul: support AVX512_BF16 insns
Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
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Jan Beulich committed
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commit
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6 files changed
+100
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@@ -550,6 +550,12 @@ static const struct test avx512_4vnniw_512[] = {
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INSN(p4dpwssds, f2, 0f38, 53, el_4, d, vl),
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};
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static const struct test avx512_bf16_all[] = {
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INSN(vcvtne2ps2bf16, f2, 0f38, 72, vl, d, vl),
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INSN(vcvtneps2bf16, f3, 0f38, 72, vl, d, vl),
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INSN(vdpbf16ps, f3, 0f38, 52, vl, d, vl),
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};
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static const struct test avx512_bitalg_all[] = {
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INSN(popcnt, 66, 0f38, 54, vl, bw, vl),
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INSN(pshufbitqmb, 66, 0f38, 8f, vl, b, vl),
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@@ -984,6 +990,7 @@ void evex_disp8_test(void *instr, struct x86_emulate_ctxt *ctxt,
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RUN(avx512pf, 512);
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RUN(avx512_4fmaps, 512);
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RUN(avx512_4vnniw, 512);
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RUN(avx512_bf16, all);
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RUN(avx512_bitalg, all);
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RUN(avx512_ifma, all);
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RUN(avx512_vbmi, all);
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@@ -4659,6 +4659,80 @@ int main(int argc, char **argv)
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else
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printf("skipped\n");
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if ( stack_exec && cpu_has_avx512_bf16 )
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{
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decl_insn(vcvtne2ps2bf16);
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decl_insn(vcvtneps2bf16);
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decl_insn(vdpbf16ps);
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static const struct {
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float f[16];
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} in1 = {{
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1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
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}}, in2 = {{
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1, -2, 3, -4, 5, -6, 7, -8, 9, -10, 11, -12, 13, -14, 15, -16
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}}, out = {{
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1 * 1 + 2 * 2, 3 * 3 + 4 * 4,
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5 * 5 + 6 * 6, 7 * 7 + 8 * 8,
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9 * 9 + 10 * 10, 11 * 11 + 12 * 12,
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13 * 13 + 14 * 14, 15 * 15 + 16 * 16,
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1 * 1 - 2 * 2, 3 * 3 - 4 * 4,
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5 * 5 - 6 * 6, 7 * 7 - 8 * 8,
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9 * 9 - 10 * 10, 11 * 11 - 12 * 12,
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13 * 13 - 14 * 14, 15 * 15 - 16 * 16
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}};
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printf("%-40s", "Testing vcvtne2ps2bf16 64(%ecx),%zmm1,%zmm2...");
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asm volatile ( "vmovups %1, %%zmm1\n"
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put_insn(vcvtne2ps2bf16,
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/* vcvtne2ps2bf16 64(%0), %%zmm1, %%zmm2 */
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".byte 0x62, 0xf2, 0x77, 0x48, 0x72, 0x51, 0x01")
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:: "c" (NULL), "m" (in2) );
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set_insn(vcvtne2ps2bf16);
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regs.ecx = (unsigned long)&in1 - 64;
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rc = x86_emulate(&ctxt, &emulops);
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if ( rc != X86EMUL_OKAY || !check_eip(vcvtne2ps2bf16) )
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goto fail;
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printf("pending\n");
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printf("%-40s", "Testing vcvtneps2bf16 64(%ecx),%ymm3...");
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asm volatile ( put_insn(vcvtneps2bf16,
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/* vcvtneps2bf16 64(%0), %%ymm3 */
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".byte 0x62, 0xf2, 0x7e, 0x48, 0x72, 0x59, 0x01")
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:: "c" (NULL) );
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set_insn(vcvtneps2bf16);
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rc = x86_emulate(&ctxt, &emulops);
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if ( rc != X86EMUL_OKAY || !check_eip(vcvtneps2bf16) )
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goto fail;
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asm ( "vmovdqa %%ymm2, %%ymm5\n\t"
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"vpcmpeqd %%zmm3, %%zmm5, %%k0\n\t"
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"kmovw %%k0, %0"
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: "=g" (rc) : "m" (out) );
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if ( rc != 0xffff )
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goto fail;
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printf("pending\n");
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printf("%-40s", "Testing vdpbf16ps 128(%ecx),%zmm2,%zmm4...");
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asm volatile ( "vmovdqa %%ymm3, %0\n\t"
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"vmovdqa %%ymm3, %1\n"
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put_insn(vdpbf16ps,
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/* vdpbf16ps 128(%2), %%zmm2, %%zmm4 */
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".byte 0x62, 0xf2, 0x6e, 0x48, 0x52, 0x61, 0x02")
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: "=&m" (res[0]), "=&m" (res[8])
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: "c" (NULL)
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: "memory" );
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set_insn(vdpbf16ps);
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regs.ecx = (unsigned long)res - 128;
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rc = x86_emulate(&ctxt, &emulops);
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if ( rc != X86EMUL_OKAY || !check_eip(vdpbf16ps) )
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goto fail;
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asm ( "vcmpeqps %1, %%zmm4, %%k0\n\t"
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"kmovw %%k0, %0"
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: "=g" (rc) : "m" (out) );
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if ( rc != 0xffff )
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goto fail;
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printf("okay\n");
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}
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printf("%-40s", "Testing invpcid 16(%ecx),%%edx...");
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if ( stack_exec )
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{
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@@ -156,6 +156,7 @@ static inline bool xcr0_mask(uint64_t mask)
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#define cpu_has_avx512_vpopcntdq (cp.feat.avx512_vpopcntdq && xcr0_mask(0xe6))
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#define cpu_has_avx512_4vnniw (cp.feat.avx512_4vnniw && xcr0_mask(0xe6))
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#define cpu_has_avx512_4fmaps (cp.feat.avx512_4fmaps && xcr0_mask(0xe6))
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#define cpu_has_avx512_bf16 (cp.feat.avx512_bf16 && xcr0_mask(0xe6))
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#define cpu_has_xgetbv1 (cpu_has_xsave && cp.xstate.xgetbv1)
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@@ -1916,6 +1916,7 @@ amd_like(const struct x86_emulate_ctxt *ctxt)
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#define vcpu_has_rdpid() (ctxt->cpuid->feat.rdpid)
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#define vcpu_has_avx512_4vnniw() (ctxt->cpuid->feat.avx512_4vnniw)
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#define vcpu_has_avx512_4fmaps() (ctxt->cpuid->feat.avx512_4fmaps)
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#define vcpu_has_avx512_bf16() (ctxt->cpuid->feat.avx512_bf16)
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#define vcpu_must_have(feat) \
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generate_exception_if(!vcpu_has_##feat(), EXC_UD)
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@@ -9029,6 +9030,19 @@ x86_emulate(
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generate_exception_if(evex.w, EXC_UD);
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goto avx512f_no_sae;
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case X86EMUL_OPC_EVEX_F2(0x0f38, 0x72): /* vcvtne2ps2bf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
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case X86EMUL_OPC_EVEX_F3(0x0f38, 0x72): /* vcvtneps2bf16 [xyz]mm/mem,{x,y}mm{k} */
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if ( evex.pfx == vex_f2 )
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fault_suppression = false;
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else
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d |= TwoOp;
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/* fall through */
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case X86EMUL_OPC_EVEX_F3(0x0f38, 0x52): /* vdpbf16ps [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
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host_and_vcpu_must_have(avx512_bf16);
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generate_exception_if(evex.w, EXC_UD);
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op_bytes = 16 << evex.lr;
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goto avx512f_no_sae;
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case X86EMUL_OPC_VEX_66(0x0f38, 0x58): /* vpbroadcastd xmm/m32,{x,y}mm */
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case X86EMUL_OPC_VEX_66(0x0f38, 0x59): /* vpbroadcastq xmm/m64,{x,y}mm */
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case X86EMUL_OPC_VEX_66(0x0f38, 0x78): /* vpbroadcastb xmm/m8,{x,y}mm */
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@@ -129,6 +129,9 @@
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#define cpu_has_avx512_4fmaps boot_cpu_has(X86_FEATURE_AVX512_4FMAPS)
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#define cpu_has_tsx_force_abort boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT)
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/* CPUID level 0x00000007:1.eax */
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#define cpu_has_avx512_bf16 boot_cpu_has(X86_FEATURE_AVX512_BF16)
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/* Synthesized. */
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#define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON)
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#define cpu_has_cpuid_faulting boot_cpu_has(X86_FEATURE_CPUID_FAULTING)
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@@ -262,7 +262,7 @@ XEN_CPUFEATURE(CORE_CAPS, 9*32+30) /* IA32_CORE_CAPABILITIES MSR */
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XEN_CPUFEATURE(SSBD, 9*32+31) /*A MSR_SPEC_CTRL.SSBD available */
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/* Intel-defined CPU features, CPUID level 0x00000007:1.eax, word 10 */
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XEN_CPUFEATURE(AVX512_BF16, 10*32+ 5) /* AVX512 BFloat16 Instructions */
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XEN_CPUFEATURE(AVX512_BF16, 10*32+ 5) /*A AVX512 BFloat16 Instructions */
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#endif /* XEN_CPUFEATURE */
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