From 8070bdfa7220e772fae248abd3cbf5e87fc0fefb Mon Sep 17 00:00:00 2001 From: Andrew Cooper Date: Tue, 4 Nov 2025 18:08:07 +0000 Subject: [PATCH] x86/amd: Mitigate AMD-SN-7052 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is XSA-490 / CVE-2025-54518. Signed-off-by: Andrew Cooper Reviewed-by: Roger Pau Monné --- xen/arch/x86/cpu/amd.c | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index 712734a6e7..70783c9a0a 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -1015,11 +1015,25 @@ static void amd_check_bp_cfg(void) { uint64_t val, new = 0; - /* - * AMD Erratum #1485. Set bit 5, as instructed. - */ - if (!cpu_has_hypervisor && boot_cpu_data.family == 0x19 && is_zen4_uarch()) - new |= (1 << 5); + if (!cpu_has_hypervisor) { + /* + * AMD Erratum #1485. If SMT is enabled and STIBP disabled, + * the CPU may fetch incorrect instruction bytes. + * + * Set bit 5, as instructed. + */ + if (boot_cpu_data.family == 0x19 && is_zen4_uarch()) + new |= (1 << 5); + + /* + * AMD SB-7052. CPU OP Cache corruption, causing instructions + * to be executed at a higher privilege. + * + * Set bit 33, as instructed. + */ + if (boot_cpu_data.family == 0x17 && is_zen2_uarch()) + new |= (1UL << 33); + } /* * On hardware supporting SRSO_MSR_FIX, activate BP_SPEC_REDUCE by