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ARM/sysctl: Expose the supported guest GIC modes in physinfo
In preparation to simplify the domain creation logic surrounding GIC version. On a GICv3 host, also report support for GICv2-compatible guests when the hardware's vGICv2 compatibility mode is enabled, rather than just the native GIC version. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Signed-off-by: Julian Vetter <julian.vetter@vates.tech> Reviewed-by: Michal Orzel <michal.orzel@amd.com>
This commit is contained in:
Andrew Cooper authored and Michal Orzel committed
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@@ -433,6 +433,12 @@ unsigned int vgic_max_vcpus(unsigned int domctl_vgic_version);
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void vgic_v2_setup_hw(paddr_t dbase, paddr_t cbase, paddr_t csize,
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paddr_t vbase, uint32_t aliased_offset);
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#ifdef CONFIG_VGICV2
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bool vgic_v2_hw_enabled(void);
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#else
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static inline bool vgic_v2_hw_enabled(void) { return false; }
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#endif
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#ifdef CONFIG_GICV3
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struct rdist_region;
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void vgic_v3_setup_hw(paddr_t dbase,
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@@ -12,7 +12,11 @@
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#include <xen/dt-overlay.h>
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#include <xen/errno.h>
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#include <xen/hypercall.h>
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#include <asm/arm64/sve.h>
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#include <asm/gic.h>
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#include <asm/vgic.h>
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#include <public/sysctl.h>
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void arch_do_physinfo(struct xen_sysctl_physinfo *pi)
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@@ -21,6 +25,31 @@ void arch_do_physinfo(struct xen_sysctl_physinfo *pi)
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pi->arch_capabilities |= MASK_INSR(sve_encode_vl(get_sys_vl_len()),
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XEN_SYSCTL_PHYSCAP_ARM_SVE_MASK);
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switch ( gic_hw_version() )
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{
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case GIC_V2:
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pi->arch_capabilities |= XEN_SYSCTL_PHYSCAP_ARM_GIC_V2;
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break;
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case GIC_V3:
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pi->arch_capabilities |= XEN_SYSCTL_PHYSCAP_ARM_GIC_V3;
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/* GICv3 may additionally support GICv2-compatible guests. */
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if ( vgic_v2_hw_enabled() )
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pi->arch_capabilities |= XEN_SYSCTL_PHYSCAP_ARM_GIC_V2;
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break;
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default:
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/*
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* Running a control domain without having the GIC sorted yet?
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* Something's broken, but there's nothing we can do about it here.
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*/
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printk_once(XENLOG_ERR "Unrecognised GIC version %d\n",
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gic_hw_version());
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ASSERT_UNREACHABLE();
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break;
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}
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}
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long arch_do_sysctl(struct xen_sysctl *sysctl,
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@@ -49,6 +49,11 @@ void __init vgic_v2_setup_hw(paddr_t dbase, paddr_t cbase, paddr_t csize,
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vgic_v2_hw.aliased_offset = aliased_offset;
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}
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bool vgic_v2_hw_enabled(void)
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{
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return vgic_v2_hw.enabled;
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}
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#define NR_TARGETS_PER_ITARGETSR 4U
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#define NR_BITS_PER_TARGET (32U / NR_TARGETS_PER_ITARGETSR)
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@@ -47,6 +47,11 @@ void __init vgic_v2_setup_hw(paddr_t dbase, paddr_t cbase, paddr_t csize,
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printk("Using the new VGIC implementation.\n");
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}
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bool vgic_v2_hw_enabled(void)
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{
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return gic_v2_hw_data.enabled;
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}
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/*
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* transfer the content of the LRs back into the corresponding ap_list:
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* - active bit is transferred as is
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@@ -106,6 +106,8 @@ struct xen_sysctl_tbuf_op {
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#if defined(__arm__) || defined(__aarch64__)
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#define XEN_SYSCTL_PHYSCAP_ARM_SVE_MASK (0x1FU)
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#define XEN_SYSCTL_PHYSCAP_ARM_GIC_V2 (1U << 5)
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#define XEN_SYSCTL_PHYSCAP_ARM_GIC_V3 (1U << 6)
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#endif
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struct xen_sysctl_physinfo {
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