mirror of
https://github.com/xen-project/xen.git
synced 2026-10-28 10:11:27 +01:00
xen/IOMMU: Switch bool_t to bool
... as part of cleaning up the types used. Minor style cleanup on some altered lines. No functional change. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Reviewed-by: Jan Beulich <jbeulich@suse.com> Acked-by: Julien Grall <jgrall@amazon.com>
This commit is contained in:
1 parent
11d9f3ddf5
commit
870d5cd9a9
16 files changed
+49
-49
No files matched your search
@@ -174,7 +174,7 @@ struct guest_iommu {
|
||||
|
||||
struct domain *domain;
|
||||
spinlock_t lock;
|
||||
bool_t enabled;
|
||||
bool enabled;
|
||||
|
||||
struct guest_dev_table dev_table;
|
||||
struct guest_buffer cmd_buffer;
|
||||
@@ -194,7 +194,7 @@ struct guest_iommu {
|
||||
struct guest_iommu_msi msi;
|
||||
};
|
||||
|
||||
extern bool_t iommuv2_enabled;
|
||||
extern bool iommuv2_enabled;
|
||||
|
||||
struct acpi_ivrs_hardware;
|
||||
|
||||
|
||||
@@ -1063,14 +1063,14 @@ static unsigned int __initdata nr_ivmd;
|
||||
#define to_ivmd_block(hdr) \
|
||||
container_of(hdr, const struct acpi_ivrs_memory, header)
|
||||
|
||||
static inline bool_t is_ivhd_block(u8 type)
|
||||
static inline bool is_ivhd_block(u8 type)
|
||||
{
|
||||
return (type == ACPI_IVRS_TYPE_HARDWARE ||
|
||||
((amd_iommu_acpi_info & ACPI_IVRS_EFR_SUP) &&
|
||||
type == ACPI_IVRS_TYPE_HARDWARE_11H));
|
||||
}
|
||||
|
||||
static inline bool_t is_ivmd_block(u8 type)
|
||||
static inline bool is_ivmd_block(u8 type)
|
||||
{
|
||||
return (type == ACPI_IVRS_TYPE_MEMORY_ALL ||
|
||||
type == ACPI_IVRS_TYPE_MEMORY_ONE ||
|
||||
@@ -1102,7 +1102,7 @@ static int __init cf_check parse_ivrs_table(struct acpi_table_header *table)
|
||||
const struct acpi_ivrs_header *ivrs_block;
|
||||
unsigned long length;
|
||||
unsigned int apic, i;
|
||||
bool_t sb_ioapic = !iommu_intremap;
|
||||
bool sb_ioapic = !iommu_intremap;
|
||||
int error = 0;
|
||||
|
||||
BUG_ON(!table);
|
||||
|
||||
@@ -34,7 +34,7 @@ unsigned int __read_mostly ivrs_bdf_entries;
|
||||
u8 __read_mostly ivhd_type;
|
||||
static struct radix_tree_root ivrs_maps;
|
||||
LIST_HEAD_READ_MOSTLY(amd_iommu_head);
|
||||
bool_t iommuv2_enabled;
|
||||
bool iommuv2_enabled;
|
||||
|
||||
bool __ro_after_init amd_iommu_perdev_intremap = true;
|
||||
|
||||
@@ -737,7 +737,7 @@ static void cf_check iommu_interrupt_handler(
|
||||
tasklet_schedule(&amd_iommu_irq_tasklet);
|
||||
}
|
||||
|
||||
static bool_t __init set_iommu_interrupt_handler(struct amd_iommu *iommu)
|
||||
static bool __init set_iommu_interrupt_handler(struct amd_iommu *iommu)
|
||||
{
|
||||
int irq, ret;
|
||||
|
||||
@@ -1329,7 +1329,7 @@ static int __init cf_check amd_iommu_setup_device_table(
|
||||
}
|
||||
|
||||
/* Check whether SP5100 SATA Combined mode is on */
|
||||
static bool_t __init amd_sp5100_erratum28(void)
|
||||
static bool __init amd_sp5100_erratum28(void)
|
||||
{
|
||||
u32 bus, id;
|
||||
u16 vendor_id, dev_id;
|
||||
|
||||
@@ -28,7 +28,7 @@
|
||||
/* dom_io is used as a sentinel for quarantined devices */
|
||||
#define QUARANTINE_SKIP(d, p) ((d) == dom_io && !(p)->arch.amd.root_table)
|
||||
|
||||
static bool_t __read_mostly init_done;
|
||||
static bool __read_mostly init_done;
|
||||
|
||||
static const struct iommu_init_ops _iommu_init_ops;
|
||||
|
||||
|
||||
@@ -18,7 +18,7 @@
|
||||
#include <xen/pci_regs.h>
|
||||
#include "ats.h"
|
||||
|
||||
bool_t __read_mostly ats_enabled = 0;
|
||||
bool __read_mostly ats_enabled;
|
||||
boolean_param("ats", ats_enabled);
|
||||
|
||||
int enable_ats_device(struct pci_dev *pdev, struct list_head *ats_list)
|
||||
|
||||
@@ -22,7 +22,7 @@
|
||||
#define ATS_QUEUE_DEPTH_MASK 0x1f
|
||||
#define ATS_ENABLE (1<<15)
|
||||
|
||||
extern bool_t ats_enabled;
|
||||
extern bool ats_enabled;
|
||||
|
||||
int enable_ats_device(struct pci_dev *pdev, struct list_head *ats_list);
|
||||
void disable_ats_device(struct pci_dev *pdev);
|
||||
|
||||
@@ -83,9 +83,9 @@ fail:
|
||||
return rc;
|
||||
}
|
||||
|
||||
static bool_t iommu_dt_device_is_assigned(const struct dt_device_node *dev)
|
||||
static bool iommu_dt_device_is_assigned(const struct dt_device_node *dev)
|
||||
{
|
||||
bool_t assigned = 0;
|
||||
bool assigned = false;
|
||||
|
||||
if ( !dt_device_is_protected(dev) )
|
||||
return 0;
|
||||
|
||||
@@ -29,7 +29,7 @@ bool __initdata iommu_enable = 1;
|
||||
bool __read_mostly iommu_enabled;
|
||||
bool __read_mostly force_iommu;
|
||||
bool __read_mostly iommu_verbose;
|
||||
static bool_t __read_mostly iommu_crash_disable;
|
||||
static bool __read_mostly iommu_crash_disable;
|
||||
|
||||
#define IOMMU_quarantine_none 0 /* aka false */
|
||||
#define IOMMU_quarantine_basic 1 /* aka true */
|
||||
@@ -59,7 +59,7 @@ bool __read_mostly iommu_hap_pt_share = true;
|
||||
|
||||
bool __read_mostly iommu_debug;
|
||||
|
||||
DEFINE_PER_CPU(bool_t, iommu_dont_flush_iotlb);
|
||||
DEFINE_PER_CPU(bool, iommu_dont_flush_iotlb);
|
||||
|
||||
static int __init cf_check parse_iommu_param(const char *s)
|
||||
{
|
||||
@@ -548,7 +548,7 @@ static int __init iommu_quarantine_init(void)
|
||||
int __init iommu_setup(void)
|
||||
{
|
||||
int rc = -ENODEV;
|
||||
bool_t force_intremap = force_iommu && iommu_intremap;
|
||||
bool force_intremap = force_iommu && iommu_intremap;
|
||||
|
||||
if ( iommu_hwdom_strict )
|
||||
iommu_hwdom_passthrough = false;
|
||||
@@ -672,7 +672,7 @@ int iommu_get_reserved_device_memory(iommu_grdm_t *func, void *ctxt)
|
||||
return iommu_call(ops, get_reserved_device_memory, func, ctxt);
|
||||
}
|
||||
|
||||
bool_t iommu_has_feature(struct domain *d, enum iommu_feature feature)
|
||||
bool iommu_has_feature(struct domain *d, enum iommu_feature feature)
|
||||
{
|
||||
return is_iommu_enabled(d) && test_bit(feature, dom_iommu(d)->features);
|
||||
}
|
||||
|
||||
@@ -62,7 +62,7 @@ void pcidevs_unlock(void)
|
||||
spin_unlock_recursive(&_pcidevs_lock);
|
||||
}
|
||||
|
||||
bool_t pcidevs_locked(void)
|
||||
bool pcidevs_locked(void)
|
||||
{
|
||||
return !!spin_is_locked(&_pcidevs_lock);
|
||||
}
|
||||
@@ -74,7 +74,7 @@ static inline struct pci_seg *get_pseg(u16 seg)
|
||||
return radix_tree_lookup(&pci_segments, seg);
|
||||
}
|
||||
|
||||
bool_t pci_known_segment(u16 seg)
|
||||
bool pci_known_segment(u16 seg)
|
||||
{
|
||||
return get_pseg(seg) != NULL;
|
||||
}
|
||||
@@ -984,7 +984,7 @@ out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
bool_t __init pci_device_detect(u16 seg, u8 bus, u8 dev, u8 func)
|
||||
bool __init pci_device_detect(u16 seg, u8 bus, u8 dev, u8 func)
|
||||
{
|
||||
u32 vendor;
|
||||
|
||||
@@ -1181,7 +1181,7 @@ static int hest_match_pci(const struct acpi_hest_aer_common *p,
|
||||
p->function == PCI_FUNC(pdev->devfn);
|
||||
}
|
||||
|
||||
static bool_t hest_match_type(const struct acpi_hest_header *hest_hdr,
|
||||
static bool hest_match_type(const struct acpi_hest_header *hest_hdr,
|
||||
const struct pci_dev *pdev)
|
||||
{
|
||||
unsigned int pos = pci_find_cap_offset(pdev->seg, pdev->bus,
|
||||
@@ -1207,10 +1207,10 @@ static bool_t hest_match_type(const struct acpi_hest_header *hest_hdr,
|
||||
|
||||
struct aer_hest_parse_info {
|
||||
const struct pci_dev *pdev;
|
||||
bool_t firmware_first;
|
||||
bool firmware_first;
|
||||
};
|
||||
|
||||
static bool_t hest_source_is_pcie_aer(const struct acpi_hest_header *hest_hdr)
|
||||
static bool hest_source_is_pcie_aer(const struct acpi_hest_header *hest_hdr)
|
||||
{
|
||||
if ( hest_hdr->type == ACPI_HEST_TYPE_AER_ROOT_PORT ||
|
||||
hest_hdr->type == ACPI_HEST_TYPE_AER_ENDPOINT ||
|
||||
@@ -1224,7 +1224,7 @@ static int cf_check aer_hest_parse(
|
||||
{
|
||||
struct aer_hest_parse_info *info = data;
|
||||
const struct acpi_hest_aer_common *p;
|
||||
bool_t ff;
|
||||
bool ff;
|
||||
|
||||
if ( !hest_source_is_pcie_aer(hest_hdr) )
|
||||
return 0;
|
||||
@@ -1254,7 +1254,7 @@ static int cf_check aer_hest_parse(
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool_t pcie_aer_get_firmware_first(const struct pci_dev *pdev)
|
||||
bool pcie_aer_get_firmware_first(const struct pci_dev *pdev)
|
||||
{
|
||||
struct aer_hest_parse_info info = { .pdev = pdev };
|
||||
|
||||
|
||||
@@ -149,7 +149,7 @@ struct vtd_iommu *ioapic_to_iommu(unsigned int apic_id)
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static bool_t acpi_hpet_device_match(
|
||||
static bool acpi_hpet_device_match(
|
||||
struct list_head *list, unsigned int hpet_id)
|
||||
{
|
||||
struct acpi_hpet_unit *hpet;
|
||||
@@ -1052,14 +1052,14 @@ void acpi_dmar_zap(void)
|
||||
write_atomic((uint32_t*)&dmar_table->signature[0], sig);
|
||||
}
|
||||
|
||||
bool_t platform_supports_intremap(void)
|
||||
bool platform_supports_intremap(void)
|
||||
{
|
||||
const unsigned int mask = ACPI_DMAR_INTR_REMAP;
|
||||
|
||||
return (dmar_flags & mask) == ACPI_DMAR_INTR_REMAP;
|
||||
}
|
||||
|
||||
bool_t __init platform_supports_x2apic(void)
|
||||
bool __init platform_supports_x2apic(void)
|
||||
{
|
||||
const unsigned int mask = ACPI_DMAR_INTR_REMAP | ACPI_DMAR_X2APIC_OPT_OUT;
|
||||
|
||||
|
||||
@@ -26,7 +26,7 @@
|
||||
#define VTDPREFIX "[VT-D]"
|
||||
|
||||
struct pci_ats_dev;
|
||||
extern bool_t rwbf_quirk;
|
||||
extern bool rwbf_quirk;
|
||||
extern const struct iommu_init_ops intel_iommu_init_ops;
|
||||
|
||||
void print_iommu_regs(struct acpi_drhd_unit *drhd);
|
||||
@@ -111,7 +111,7 @@ int __must_check me_wifi_quirk(struct domain *domain, uint8_t bus,
|
||||
void pci_vtd_quirk(const struct pci_dev *);
|
||||
void quirk_iommu_caps(struct vtd_iommu *iommu);
|
||||
|
||||
bool_t platform_supports_intremap(void);
|
||||
bool_t platform_supports_x2apic(void);
|
||||
bool platform_supports_intremap(void);
|
||||
bool platform_supports_x2apic(void);
|
||||
|
||||
#endif // _VTD_EXTERN_H_
|
||||
@@ -644,8 +644,8 @@ static int __must_check iommu_flush_iotlb_global(struct vtd_iommu *iommu,
|
||||
}
|
||||
|
||||
static int __must_check iommu_flush_iotlb_dsi(struct vtd_iommu *iommu, u16 did,
|
||||
bool_t flush_non_present_entry,
|
||||
bool_t flush_dev_iotlb)
|
||||
bool flush_non_present_entry,
|
||||
bool flush_dev_iotlb)
|
||||
{
|
||||
int status;
|
||||
|
||||
@@ -663,8 +663,8 @@ static int __must_check iommu_flush_iotlb_dsi(struct vtd_iommu *iommu, u16 did,
|
||||
|
||||
static int __must_check iommu_flush_iotlb_psi(struct vtd_iommu *iommu, u16 did,
|
||||
u64 addr, unsigned int order,
|
||||
bool_t flush_non_present_entry,
|
||||
bool_t flush_dev_iotlb)
|
||||
bool flush_non_present_entry,
|
||||
bool flush_dev_iotlb)
|
||||
{
|
||||
int status;
|
||||
|
||||
@@ -694,7 +694,7 @@ static int __must_check iommu_flush_all(void)
|
||||
{
|
||||
struct acpi_drhd_unit *drhd;
|
||||
struct vtd_iommu *iommu;
|
||||
bool_t flush_dev_iotlb;
|
||||
bool flush_dev_iotlb;
|
||||
int rc = 0;
|
||||
|
||||
flush_local(FLUSH_CACHE);
|
||||
@@ -736,7 +736,7 @@ static int __must_check cf_check iommu_flush_iotlb(struct domain *d, dfn_t dfn,
|
||||
struct domain_iommu *hd = dom_iommu(d);
|
||||
struct acpi_drhd_unit *drhd;
|
||||
struct vtd_iommu *iommu;
|
||||
bool_t flush_dev_iotlb;
|
||||
bool flush_dev_iotlb;
|
||||
int iommu_domid;
|
||||
int ret = 0;
|
||||
|
||||
@@ -1480,7 +1480,7 @@ int domain_context_mapping_one(
|
||||
uint16_t seg = iommu->drhd->segment, prev_did = 0;
|
||||
struct domain *prev_dom = NULL;
|
||||
int rc, ret;
|
||||
bool_t flush_dev_iotlb;
|
||||
bool flush_dev_iotlb;
|
||||
|
||||
if ( QUARANTINE_SKIP(domain, pgd_maddr) )
|
||||
return 0;
|
||||
@@ -1874,7 +1874,7 @@ int domain_context_unmap_one(
|
||||
struct context_entry *context, *context_entries;
|
||||
u64 maddr;
|
||||
int iommu_domid, rc, ret;
|
||||
bool_t flush_dev_iotlb;
|
||||
bool flush_dev_iotlb;
|
||||
|
||||
ASSERT(pcidevs_locked());
|
||||
spin_lock(&iommu->lock);
|
||||
@@ -2873,7 +2873,7 @@ static int cf_check intel_iommu_assign_device(
|
||||
if ( rmrr->segment == seg && bdf == PCI_BDF(bus, devfn) &&
|
||||
rmrr->scope.devices_cnt > 1 )
|
||||
{
|
||||
bool_t relaxed = !!(flag & XEN_DOMCTL_DEV_RDM_RELAXED);
|
||||
bool relaxed = flag & XEN_DOMCTL_DEV_RDM_RELAXED;
|
||||
|
||||
printk(XENLOG_GUEST "%s" VTDPREFIX
|
||||
" It's %s to assign %pp"
|
||||
|
||||
@@ -152,7 +152,7 @@ static int __must_check queue_invalidate_iotlb_sync(struct vtd_iommu *iommu,
|
||||
|
||||
static int __must_check queue_invalidate_wait(struct vtd_iommu *iommu,
|
||||
u8 iflag, u8 sw, u8 fn,
|
||||
bool_t flush_dev_iotlb)
|
||||
bool flush_dev_iotlb)
|
||||
{
|
||||
static DEFINE_PER_CPU(uint32_t, poll_slot);
|
||||
unsigned int index;
|
||||
|
||||
@@ -56,9 +56,9 @@ static unsigned int snb_igd_timeout;
|
||||
|
||||
static u32 __read_mostly ioh_id;
|
||||
static u32 __initdata igd_id;
|
||||
bool_t __read_mostly rwbf_quirk;
|
||||
static bool_t __read_mostly is_cantiga_b3;
|
||||
static bool_t __read_mostly is_snb_gfx;
|
||||
bool __read_mostly rwbf_quirk;
|
||||
static bool __read_mostly is_cantiga_b3;
|
||||
static bool __read_mostly is_snb_gfx;
|
||||
static u8 *__read_mostly igd_reg_va;
|
||||
static spinlock_t igd_lock;
|
||||
|
||||
@@ -498,7 +498,7 @@ void pci_vtd_quirk(const struct pci_dev *pdev)
|
||||
int seg = pdev->seg;
|
||||
int bus = pdev->bus;
|
||||
int pos;
|
||||
bool_t ff;
|
||||
bool ff;
|
||||
u32 val, val2;
|
||||
u64 bar;
|
||||
paddr_t pa;
|
||||
|
||||
@@ -119,7 +119,7 @@ int dev_invalidate_iotlb(struct vtd_iommu *iommu, u16 did,
|
||||
|
||||
list_for_each_entry_safe( pdev, temp, &iommu->ats_devices, ats.list )
|
||||
{
|
||||
bool_t sbit;
|
||||
bool sbit;
|
||||
int rc = 0;
|
||||
|
||||
switch ( type )
|
||||
|
||||
@@ -46,7 +46,7 @@ static inline dfn_t dfn_add(dfn_t dfn, unsigned long i)
|
||||
return _dfn(dfn_x(dfn) + i);
|
||||
}
|
||||
|
||||
static inline bool_t dfn_eq(dfn_t x, dfn_t y)
|
||||
static inline bool dfn_eq(dfn_t x, dfn_t y)
|
||||
{
|
||||
return dfn_x(x) == dfn_x(y);
|
||||
}
|
||||
@@ -193,7 +193,7 @@ enum iommu_feature
|
||||
IOMMU_FEAT_count
|
||||
};
|
||||
|
||||
bool_t iommu_has_feature(struct domain *d, enum iommu_feature feature);
|
||||
bool iommu_has_feature(struct domain *d, enum iommu_feature feature);
|
||||
|
||||
#ifdef CONFIG_HAS_PCI
|
||||
struct pirq;
|
||||
@@ -409,7 +409,7 @@ void iommu_dev_iotlb_flush_timeout(struct domain *d, struct pci_dev *pdev);
|
||||
* iommu_iotlb_flush/iommu_iotlb_flush_all will be explicitly called by
|
||||
* the caller.
|
||||
*/
|
||||
DECLARE_PER_CPU(bool_t, iommu_dont_flush_iotlb);
|
||||
DECLARE_PER_CPU(bool, iommu_dont_flush_iotlb);
|
||||
|
||||
extern struct spinlock iommu_pt_cleanup_lock;
|
||||
extern struct page_list_head iommu_pt_cleanup_list;
|
||||
|
||||