From 87a8a5728e5936f088c94bd7960c70f9b1cef36e Mon Sep 17 00:00:00 2001 From: Michal Orzel Date: Tue, 11 Aug 2026 15:08:18 +0200 Subject: [PATCH] xen/arm: drop incorrect EL0 accessibility comments for PMINTEN{SET,CLR} The comments on the PMINTENSET/PMINTENCLR cases claim that an EL0 access may be trapped to EL2 when MDCR_EL2.TPM is set, and that such a case is handled. Both are inaccurate. PMINTENSET_EL1/PMINTENCLR_EL1 are accessible at EL1 and above only, with no enable making them accessible at EL0. Arm ARM (DDI 0487M.b) D1.4.5.6 "Prioritization of Synchronous exceptions" orders the two exceptions. An access that is never accessible at the current Exception level regardless of any enables or traps is priority 18, whereas an exception taken to EL2 as the result of a configuration control in MDCR_EL2 is priority 24. An EL0 access is therefore UNDEFINED and taken to EL1. Signed-off-by: Michal Orzel Reviewed-by: Stefano Stabellini --- xen/arch/arm/arm64/vsysreg.c | 4 ---- xen/arch/arm/vcpreg.c | 1 - 2 files changed, 5 deletions(-) diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c index d55a538ec4..d9e3619dfb 100644 --- a/xen/arch/arm/arm64/vsysreg.c +++ b/xen/arch/arm/arm64/vsysreg.c @@ -227,10 +227,6 @@ void do_sysreg(struct cpu_user_regs *regs, */ case HSR_SYSREG_PMINTENSET_EL1: case HSR_SYSREG_PMINTENCLR_EL1: - /* - * Accessible from EL1 only, but if EL0 trap happens handle as - * undef. - */ return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); case HSR_SYSREG_PMUSERENR_EL0: /* RO at EL0. RAZ/WI at EL1 */ diff --git a/xen/arch/arm/vcpreg.c b/xen/arch/arm/vcpreg.c index 59a2b89a0e..3205c7df46 100644 --- a/xen/arch/arm/vcpreg.c +++ b/xen/arch/arm/vcpreg.c @@ -292,7 +292,6 @@ void do_cp15_32(struct cpu_user_regs *regs, const union hsr hsr) return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); case HSR_CPREG32(PMINTENSET): case HSR_CPREG32(PMINTENCLR): - /* EL1 only, however MDCR_EL2.TPM==1 means EL0 may trap here also. */ return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); case HSR_CPREG32(PMCR): case HSR_CPREG32(PMCNTENSET):