diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c index 597befa387..ab86c75355 100644 --- a/xen/arch/x86/acpi/cpu_idle.c +++ b/xen/arch/x86/acpi/cpu_idle.c @@ -296,6 +296,9 @@ void mwait_idle_with_hints(unsigned int eax, unsigned int ecx) unsigned int cpu = smp_processor_id(); s_time_t expires = per_cpu(timer_deadline, cpu); + if ( boot_cpu_has(X86_FEATURE_CLFLUSH_MONITOR) ) + clflush((void *)&mwait_wakeup(cpu)); + __monitor((void *)&mwait_wakeup(cpu), 0, 0); smp_mb(); diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c index 9e02cf61b8..e178b5c418 100644 --- a/xen/arch/x86/cpu/intel.c +++ b/xen/arch/x86/cpu/intel.c @@ -148,6 +148,9 @@ void __devinit early_intel_workaround(struct cpuinfo_x86 *c) /* * P4 Xeon errata 037 workaround. * Hardware prefetcher may cause stale data to be loaded into the cache. + * + * Xeon 7400 erratum AAI65 (and further newer Xeons) + * MONITOR/MWAIT may have excessive false wakeups */ static void __devinit Intel_errata_workarounds(struct cpuinfo_x86 *c) { @@ -162,6 +165,10 @@ static void __devinit Intel_errata_workarounds(struct cpuinfo_x86 *c) wrmsr (MSR_IA32_MISC_ENABLE, lo, hi); } } + + if (c->x86 == 6 && cpu_has_clflush && + (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47)) + set_bit(X86_FEATURE_CLFLUSH_MONITOR, c->x86_capability); } diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h index f38fde43ce..4bb5c69390 100644 --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -71,6 +71,7 @@ #define X86_FEATURE_TSC_RELIABLE (3*32+12) /* TSC is known to be reliable */ #define X86_FEATURE_XTOPOLOGY (3*32+13) /* cpu topology enum extensions */ #define X86_FEATURE_CPUID_FAULTING (3*32+14) /* cpuid faulting */ +#define X86_FEATURE_CLFLUSH_MONITOR (3*32+15) /* clflush reqd with monitor */ /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ #define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */