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xen/arm: Clean up 32bit arm_smccc_1_1_smc()
... before making a related copy of it. * Drop __constraints() so the output parameters are visible in the same block as they're defined. Use PASTE() rather than opencoding it. * Adjust the indentation of trailing \'s for consistency. * Drop the newline at the end of the instruction. * Indent the if condition correctly. ___res is always of type arm_smccc_res (declared in __declare_arg_0()), so drop the typeof(). * Drop arm_smccc_1_0_smc() as it has no users. No functional change. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>
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Andrew Cooper committed
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1 file changed
+22
-23
@@ -56,6 +56,8 @@
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#ifndef __ASSEMBLER__
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#include <xen/macros.h>
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extern uint32_t smccc_ver;
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/* Check if this is fast call. */
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@@ -115,24 +117,24 @@ struct arm_smccc_res {
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* This is manual register scheduling for the asm() statement, and any other
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* logic to evaluate may clobber the already-scheduled registers.
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*/
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#define __declare_arg_0(a0, res) \
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auto __a0 = (uint32_t)(a0); \
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struct arm_smccc_res *___res = (res); \
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#define __declare_arg_0(a0, res) \
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auto __a0 = (uint32_t)(a0); \
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struct arm_smccc_res *___res = (res); \
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register unsigned long arg0 ASM_REG(0) = __a0
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#define __declare_arg_1(a0, a1, res) \
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auto __a1 = (a1); \
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__declare_arg_0(a0, res); \
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#define __declare_arg_1(a0, a1, res) \
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auto __a1 = (a1); \
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__declare_arg_0(a0, res); \
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register auto arg1 ASM_REG(1) = __a1
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#define __declare_arg_2(a0, a1, a2, res) \
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auto __a2 = (a2); \
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__declare_arg_1(a0, a1, res); \
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#define __declare_arg_2(a0, a1, a2, res) \
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auto __a2 = (a2); \
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__declare_arg_1(a0, a1, res); \
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register auto arg2 ASM_REG(2) = __a2
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#define __declare_arg_3(a0, a1, a2, a3, res) \
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auto __a3 = (a3); \
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__declare_arg_2(a0, a1, a2, res); \
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#define __declare_arg_3(a0, a1, a2, a3, res) \
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auto __a3 = (a3); \
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__declare_arg_2(a0, a1, a2, res); \
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register auto arg3 ASM_REG(3) = __a3
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#define __declare_arg_4(a0, a1, a2, a3, a4, res) \
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@@ -158,12 +160,6 @@ struct arm_smccc_res {
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#define ___declare_args(count, ...) __declare_arg_ ## count(__VA_ARGS__)
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#define __declare_args(count, ...) ___declare_args(count, __VA_ARGS__)
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#define ___constraints(count) \
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: "=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3) \
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: __constraint_read_ ## count \
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: "memory"
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#define __constraints(count) ___constraints(count)
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/*
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* arm_smccc_1_1_smc() - make an SMCCC v1.1 compliant SMC call
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*
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@@ -189,10 +185,14 @@ struct arm_smccc_res {
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register unsigned long r2 ASM_REG(2); \
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register unsigned long r3 ASM_REG(3); \
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__declare_args(__count_args(__VA_ARGS__), __VA_ARGS__); \
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asm volatile("smc #0\n" \
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__constraints(__count_args(__VA_ARGS__))); \
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asm volatile ( \
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"smc #0" \
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: "=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3) \
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: PASTE(__constraint_read_, \
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__count_args(__VA_ARGS__)) \
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: "memory" ); \
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if ( ___res ) \
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*___res = (typeof(*___res)){r0, r1, r2, r3}; \
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*___res = (struct arm_smccc_res){ r0, r1, r2, r3 }; \
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} while ( 0 )
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/*
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@@ -200,7 +200,6 @@ struct arm_smccc_res {
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* v1.1.
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*/
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#ifdef CONFIG_ARM_32
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#define arm_smccc_1_0_smc(...) arm_smccc_1_1_smc(__VA_ARGS__)
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#define arm_smccc_smc(...) arm_smccc_1_1_smc(__VA_ARGS__)
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/* Make an SMCCC v1.1 compliant SMC call with guest register state. */
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@@ -217,7 +216,7 @@ static inline void arm_smccc_guest_smc(struct cpu_user_regs *regs)
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regs->r3 = res.a3;
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}
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#else
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#else /* CONFIG_ARM_64 */
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void __arm_smccc_1_0_smc(register_t a0, register_t a1, register_t a2,
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register_t a3, register_t a4, register_t a5,
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