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xen/arm32: head: Replace load_paddr with adr_l when they are equivalent
Before the MMU is turned on, PC uses physical address. Thus, one can use adr_l instead of load_paddr to obtain the physical address of a symbol. The only exception (for this replacement) is create_table_entry() which is called before and after MMU is turned on. Also, in lookup_processor_type() "r10" is no longer used. The reason being __lookup_processor_type uses adr_l (thus r10 is no longer used to obtain the physical address offset). Consequently, there is no need to save/restore r10. Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@amd.com> Reviewed-by: Michal Orzel <michal.orzel@amd.com> [jgrall: Reword comment on top of __lookup_processor_type] Signed-off-by: Julien Grall <jgrall@amazon.com>
This commit is contained in:
Ayan Kumar Halder authored and Julien Grall committed
1 parent
046f13a2b3
commit
9b807e23e7
1 file changed
+8
-11
@@ -171,7 +171,7 @@ past_zImage:
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/* Using the DTB in the .dtb section? */
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.ifnes CONFIG_DTB_FILE,""
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load_paddr r8, _sdtb
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adr_l r8, _sdtb
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.endif
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/* Initialize the UART if earlyprintk has been enabled. */
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@@ -213,7 +213,7 @@ GLOBAL(init_secondary)
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mrc CP32(r1, MPIDR)
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bic r7, r1, #(~MPIDR_HWID_MASK) /* Mask out flags to get CPU ID */
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load_paddr r0, smp_up_cpu
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adr_l r0, smp_up_cpu
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dsb
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2: ldr r1, [r0]
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cmp r1, r7
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@@ -479,7 +479,7 @@ create_page_tables:
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* create_table_entry_paddr() will clobber the register storing
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* the physical address of the table to point to.
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*/
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load_paddr r5, boot_third
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adr_l r5, boot_third
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mov_w r4, XEN_VIRT_START
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.rept XEN_NR_ENTRIES(2)
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mov r0, r5 /* r0 := paddr(l3 table) */
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@@ -578,7 +578,7 @@ enable_mmu:
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flush_xen_tlb_local r0
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/* Write Xen's PT's paddr into the HTTBR */
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load_paddr r0, boot_pgtable
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adr_l r0, boot_pgtable
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mov r1, #0 /* r0:r1 is paddr (boot_pagetable) */
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mcrr CP64(r0, r1, HTTBR)
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isb
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@@ -876,11 +876,10 @@ putn: mov pc, lr
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/* This provides a C-API version of __lookup_processor_type */
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ENTRY(lookup_processor_type)
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stmfd sp!, {r4, r10, lr}
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mov r10, #0 /* r10 := offset between virt&phys */
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stmfd sp!, {r4, lr}
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bl __lookup_processor_type
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mov r0, r1
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ldmfd sp!, {r4, r10, pc}
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ldmfd sp!, {r4, pc}
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/*
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* Read processor ID register (CP#15, CR0), and Look up in the linker-built
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@@ -888,8 +887,6 @@ ENTRY(lookup_processor_type)
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* the __proc_info lists since we aren't running with the MMU on (and therefore,
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* we are not in correct address space). We have to calculate the offset.
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*
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* r10: offset between virt&phys
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*
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* Returns:
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* r0: CPUID
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* r1: proc_info pointer
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@@ -897,8 +894,8 @@ ENTRY(lookup_processor_type)
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*/
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__lookup_processor_type:
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mrc CP32(r0, MIDR) /* r0 := our cpu id */
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load_paddr r1, __proc_info_start
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load_paddr r2, __proc_info_end
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adr_l r1, __proc_info_start
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adr_l r2, __proc_info_end
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1: ldr r3, [r1, #PROCINFO_cpu_mask]
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and r4, r0, r3 /* r4 := our cpu id with mask */
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ldr r3, [r1, #PROCINFO_cpu_val] /* r3 := cpu val in current proc info */
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