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x86/spec-ctrl: Enable Zen2 chickenbit
... as instructed in the Branch Type Confusion whitepaper. This is part of XSA-407. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
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@@ -731,6 +731,31 @@ void amd_init_ssbd(const struct cpuinfo_x86 *c)
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printk_once(XENLOG_ERR "No SSBD controls available\n");
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}
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/*
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* On Zen2 we offer this chicken (bit) on the altar of Speculation.
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*
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* Refer to the AMD Branch Type Confusion whitepaper:
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* https://XXX
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*
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* Setting this unnamed bit supposedly causes prediction information on
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* non-branch instructions to be ignored. It is to be set unilaterally in
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* newer microcode.
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*
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* This chickenbit is something unrelated on Zen1, and Zen1 vs Zen2 isn't a
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* simple model number comparison, so use STIBP as a heuristic to separate the
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* two uarches in Fam17h(AMD)/18h(Hygon).
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*/
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void amd_init_spectral_chicken(void)
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{
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uint64_t val, chickenbit = 1 << 1;
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if (cpu_has_hypervisor || !boot_cpu_has(X86_FEATURE_AMD_STIBP))
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return;
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if (rdmsr_safe(MSR_AMD64_DE_CFG2, val) == 0 && !(val & chickenbit))
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wrmsr_safe(MSR_AMD64_DE_CFG2, val | chickenbit);
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}
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void __init detect_zen2_null_seg_behaviour(void)
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{
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uint64_t base;
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@@ -796,6 +821,9 @@ static void cf_check init_amd(struct cpuinfo_x86 *c)
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amd_init_ssbd(c);
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if (c->x86 == 0x17)
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amd_init_spectral_chicken();
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/* Probe for NSCB on Zen2 CPUs when not virtualised */
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if (!cpu_has_hypervisor && !cpu_has_nscb && c == &boot_cpu_data &&
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c->x86 == 0x17)
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@@ -22,4 +22,5 @@ void cf_check early_init_amd(struct cpuinfo_x86 *c);
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void amd_log_freq(const struct cpuinfo_x86 *c);
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void amd_init_lfence(struct cpuinfo_x86 *c);
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void amd_init_ssbd(const struct cpuinfo_x86 *c);
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void amd_init_spectral_chicken(void);
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void detect_zen2_null_seg_behaviour(void);
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@@ -40,6 +40,12 @@ static void cf_check init_hygon(struct cpuinfo_x86 *c)
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c->x86 == 0x18)
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detect_zen2_null_seg_behaviour();
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/*
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* TODO: Check heuristic safety with Hygon first
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if (c->x86 == 0x18)
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amd_init_spectral_chicken();
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*/
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/*
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* Hygon CPUs before Zen2 don't clear segment bases/limits when
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* loading a NULL selector.
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@@ -377,6 +377,7 @@
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#define MSR_AMD64_DE_CFG 0xc0011029
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#define AMD64_DE_CFG_LFENCE_SERIALISE (_AC(1, ULL) << 1)
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#define MSR_AMD64_EX_CFG 0xc001102c
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#define MSR_AMD64_DE_CFG2 0xc00110e3
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#define MSR_AMD64_DR0_ADDRESS_MASK 0xc0011027
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#define MSR_AMD64_DR1_ADDRESS_MASK 0xc0011019
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