From 9ed72c697be1841e0f72628bec6c3af063050d2e Mon Sep 17 00:00:00 2001
From: Frediano Ziglio <frediano.ziglio@cloud.com>
Date: Tue, 7 Jul 2026 10:14:53 +0200
Subject: [PATCH] x86: Fix typo in comment (indicies -> indices)

Signed-off-by: Frediano Ziglio <frediano.ziglio@cloud.com>
Acked-by: Jan Beulich <jbeulich@suse.com>
---
 xen/arch/x86/traps-setup.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/x86/traps-setup.c b/xen/arch/x86/traps-setup.c
index a79a3b2013..3fe79ff0d0 100644
--- a/xen/arch/x86/traps-setup.c
+++ b/xen/arch/x86/traps-setup.c
@@ -245,7 +245,7 @@ static void __init init_ler(void)
 
     /*
      * Intel Pentium 4 is the only known CPU to not use the architectural MSR
-     * indicies.
+     * indices.
      */
     switch ( boot_cpu_data.vendor )
     {