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x86/nmi: Misc style fixes
* Drop trailing whitespace * Sort includes, dropping asm/mc146818rtc.h and asm/div64.h as unused * Brace position, and types No functional change. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Jan Beulich <jbeulich@suse.com>
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Andrew Cooper committed
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+20
-21
@@ -13,26 +13,25 @@
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* Mikael Pettersson : PM converted to driver model. Disable/enable API.
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*/
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#include <xen/console.h>
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#include <xen/cpu.h>
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#include <xen/delay.h>
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#include <xen/init.h>
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#include <xen/irq.h>
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#include <xen/keyhandler.h>
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#include <xen/lib.h>
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#include <xen/mm.h>
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#include <xen/param.h>
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#include <xen/irq.h>
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#include <xen/delay.h>
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#include <xen/time.h>
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#include <xen/sched.h>
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#include <xen/console.h>
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#include <xen/smp.h>
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#include <xen/keyhandler.h>
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#include <xen/time.h>
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#include <xen/watchdog.h>
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#include <xen/cpu.h>
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#include <asm/current.h>
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#include <asm/mc146818rtc.h>
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#include <asm/msr.h>
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#include <asm/mpspec.h>
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#include <asm/nmi.h>
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#include <asm/div64.h>
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#include <asm/apic.h>
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#include <asm/current.h>
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#include <asm/mpspec.h>
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#include <asm/msr.h>
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#include <asm/nmi.h>
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unsigned int nmi_watchdog = NMI_NONE;
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static unsigned int nmi_hz = HZ;
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@@ -199,8 +198,9 @@ static void cf_check nmi_timer_fn(void *unused)
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void disable_lapic_nmi_watchdog(void)
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{
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if (nmi_active <= 0)
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if ( nmi_active <= 0 )
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return;
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switch ( boot_cpu_data.vendor )
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{
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case X86_VENDOR_AMD:
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@@ -231,9 +231,7 @@ void disable_lapic_nmi_watchdog(void)
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static void clear_msr_range(unsigned int base, unsigned int n)
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{
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unsigned int i;
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for (i = 0; i < n; i++)
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for ( unsigned int i = 0; i < n; i++ )
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wrmsrns(base + i, 0);
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}
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@@ -302,7 +300,7 @@ static void setup_p4_watchdog(void)
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uint64_t misc_enable;
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rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
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if (!(misc_enable & MSR_IA32_MISC_ENABLE_PERF_AVAIL))
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if ( !(misc_enable & MSR_IA32_MISC_ENABLE_PERF_AVAIL) )
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return;
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nmi_perfctr_msr = MSR_P4_IQ_PERFCTR0;
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@@ -310,7 +308,7 @@ static void setup_p4_watchdog(void)
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if ( boot_cpu_data.x86_num_siblings == 2 )
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nmi_p4_cccr_val |= P4_CCCR_OVF_PMI1;
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if (!(misc_enable & MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL))
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if ( !(misc_enable & MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL) )
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clear_msr_range(0x3F1, 2);
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/* MSR 0x3F0 seems to have a default value of 0xFC00, but current
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docs doesn't fully define it, so leave it alone for now. */
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@@ -389,7 +387,7 @@ static int cf_check cpu_nmi_callback(
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}
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static struct notifier_block cpu_nmi_nfb = {
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.notifier_call = cpu_nmi_callback
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.notifier_call = cpu_nmi_callback,
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};
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static DEFINE_PER_CPU(unsigned int, last_irq_sums);
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@@ -440,7 +438,7 @@ bool nmi_watchdog_tick(const struct cpu_user_regs *regs)
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* before doing the oops ...
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*/
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this_cpu(alert_counter)++;
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if ( this_cpu(alert_counter) == opt_watchdog_timeout*nmi_hz )
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if ( this_cpu(alert_counter) == opt_watchdog_timeout * nmi_hz )
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{
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console_force_unlock();
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printk("Watchdog timer detects that CPU%d is stuck!\n",
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@@ -508,7 +506,8 @@ bool nmi_watchdog_tick(const struct cpu_user_regs *regs)
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void self_nmi(void)
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{
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unsigned long flags;
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u32 id = get_apic_id();
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uint32_t id = get_apic_id();
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local_irq_save(flags);
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apic_wait_icr_idle();
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apic_icr_write(APIC_DM_NMI | APIC_DEST_PHYSICAL, id);
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