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x86/apic: Drop sync_Arb_IDs()
It is not obvious at first glance, but this is dead logic. On Intel, xAPIC (which is what modern_apic() is really checking for) predates 64bit support, while the Family 0xf check on AMD is the K8 processor. Simply drop the logic, rather than trying to adjust vendor/family logic. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Reviewed-by: Jan Beulich <jbeulich@suse.com>
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@@ -91,23 +91,6 @@ static enum apic_mode apic_boot_mode = APIC_MODE_INVALID;
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bool __read_mostly x2apic_enabled;
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bool __read_mostly directed_eoi_enabled;
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static int modern_apic(void)
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{
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unsigned int lvr, version;
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/* AMD systems use old APIC versions, so check the CPU */
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if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
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boot_cpu_data.x86 >= 0xf)
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return 1;
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/* Hygon systems use modern APIC */
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if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
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return 1;
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lvr = apic_read(APIC_LVR);
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version = GET_APIC_VERSION(lvr);
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return version >= 0x14;
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}
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/*
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* 'what should we do if we get a hw irq event on an illegal vector'.
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* each architecture has to answer this themselves.
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@@ -396,21 +379,6 @@ int __init verify_local_APIC(void)
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return 1;
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}
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void __init sync_Arb_IDs(void)
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{
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/* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1
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And not needed on AMD */
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if (modern_apic())
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return;
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/*
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* Wait for idle.
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*/
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apic_wait_icr_idle();
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apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
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apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG | APIC_DM_INIT);
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}
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/*
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* An initial setup of the virtual wire mode.
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*/
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@@ -166,7 +166,6 @@ extern void disconnect_bsp_APIC (int virt_wire_setup);
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extern void disable_local_APIC (void);
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extern int verify_local_APIC (void);
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extern void cache_APIC_registers (void);
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extern void sync_Arb_IDs (void);
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extern void init_bsp_APIC (void);
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extern void setup_local_APIC(bool bsp);
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extern void init_apic_mappings (void);
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@@ -2163,7 +2163,7 @@ void __init setup_IO_APIC(void)
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*/
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if (!acpi_ioapic)
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setup_ioapic_ids_from_mpc();
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sync_Arb_IDs();
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setup_IO_APIC_irqs();
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init_IO_APIC_traps();
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check_timer();
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