diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig
index 2939db429b..3eddc9c1e6 100644
--- a/xen/arch/arm/Kconfig
+++ b/xen/arch/arm/Kconfig
@@ -383,6 +383,27 @@ config ARM64_ERRATUM_1508412
 
 	  If unsure, say Y.
 
+config ARM64_ERRATUM_CVE_2025_10263
+	bool "Cortex-*/Neoverse-*/C1-*: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
+	default y
+	depends on ARM_64
+	select ARM64_WORKAROUND_REPEAT_TLBI
+	help
+	  This option adds a workaround for CVE-2025-10263.
+
+	  A broadcast TLBI on another PE may complete before affected memory
+	  accesses are globally observed. This may permit bypass of Stage 1
+	  translation, Stage-2 translation, or GPT protection.
+
+	  The workaround repeats the TLBI VALE2IS, XZR + DSB ISH operation for all
+	  the broadcast TLB flush operations. A single additional TLBI and DSB are
+	  sufficient regardless of how many TLBIs are completed by the DSB.
+
+	  Note that software workarounds are required at all execution levels for
+	  affected parts to fully mitigate this issue.
+
+	  If unsure, say Y.
+
 endmenu
 
 config ARM64_HARDEN_BRANCH_PREDICTOR
diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c
index 9137958fb6..99517b5298 100644
--- a/xen/arch/arm/cpuerrata.c
+++ b/xen/arch/arm/cpuerrata.c
@@ -536,6 +536,92 @@ static const struct arm_cpu_capabilities arm_errata[] = {
         MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 3 << MIDR_VARIANT_SHIFT),
     },
 #endif
+#ifdef CONFIG_ARM64_ERRATUM_CVE_2025_10263
+    {
+        .capability = ARM64_WORKAROUND_REPEAT_TLBI,
+        MIDR_ALL_VERSIONS(MIDR_CORTEX_A76),
+    },
+    {
+        .capability = ARM64_WORKAROUND_REPEAT_TLBI,
+        MIDR_ALL_VERSIONS(MIDR_CORTEX_A76AE),
+    },
+    {
+        .capability = ARM64_WORKAROUND_REPEAT_TLBI,
+        MIDR_ALL_VERSIONS(MIDR_CORTEX_A77),
+    },
+    {
+        .capability = ARM64_WORKAROUND_REPEAT_TLBI,
+        MIDR_ALL_VERSIONS(MIDR_CORTEX_A78),
+    },
+    {
+        .capability = ARM64_WORKAROUND_REPEAT_TLBI,
+        MIDR_ALL_VERSIONS(MIDR_CORTEX_A78AE),
+    },
+    {
+        .capability = ARM64_WORKAROUND_REPEAT_TLBI,
+        MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C),
+    },
+    {
+        .capability = ARM64_WORKAROUND_REPEAT_TLBI,
+        MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
+    },
+    {
+        .capability = ARM64_WORKAROUND_REPEAT_TLBI,
+        MIDR_ALL_VERSIONS(MIDR_CORTEX_X1),
+    },
+    {
+        .capability = ARM64_WORKAROUND_REPEAT_TLBI,
+        MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C),
+    },
+    {
+        .capability = ARM64_WORKAROUND_REPEAT_TLBI,
+        MIDR_ALL_VERSIONS(MIDR_CORTEX_X2),
+    },
+    {
+        .capability = ARM64_WORKAROUND_REPEAT_TLBI,
+        MIDR_ALL_VERSIONS(MIDR_CORTEX_X3),
+    },
+    {
+        .capability = ARM64_WORKAROUND_REPEAT_TLBI,
+        MIDR_ALL_VERSIONS(MIDR_CORTEX_X4),
+    },
+    {
+        .capability = ARM64_WORKAROUND_REPEAT_TLBI,
+        MIDR_ALL_VERSIONS(MIDR_CORTEX_X925),
+    },
+    {
+        .capability = ARM64_WORKAROUND_REPEAT_TLBI,
+        MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),
+    },
+    {
+        .capability = ARM64_WORKAROUND_REPEAT_TLBI,
+        MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
+    },
+    {
+        .capability = ARM64_WORKAROUND_REPEAT_TLBI,
+        MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),
+    },
+    {
+        .capability = ARM64_WORKAROUND_REPEAT_TLBI,
+        MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2),
+    },
+    {
+        .capability = ARM64_WORKAROUND_REPEAT_TLBI,
+        MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3),
+    },
+    {
+        .capability = ARM64_WORKAROUND_REPEAT_TLBI,
+        MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3AE),
+    },
+    {
+        .capability = ARM64_WORKAROUND_REPEAT_TLBI,
+        MIDR_ALL_VERSIONS(MIDR_C1_ULTRA),
+    },
+    {
+        .capability = ARM64_WORKAROUND_REPEAT_TLBI,
+        MIDR_ALL_VERSIONS(MIDR_C1_PREMIUM),
+    },
+#endif
 #ifdef CONFIG_ARM64_HARDEN_BRANCH_PREDICTOR
     {
         .capability = ARM_HARDEN_BRANCH_PREDICTOR,