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xen/arm: Add support for GIC v3
Add support for GIC v3 specification System register access(SRE) is enabled to access cpu and virtual interface registers based on kernel GICv3 driver. This patch adds only basic v3 support. Does not support Interrupt Translation support (ITS) Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com> Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
This commit is contained in:
Vijaya Kumar K authored and Ian Campbell committed
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commit
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7 files changed
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@@ -11,6 +11,7 @@ obj-y += domctl.o
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obj-y += sysctl.o
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obj-y += domain_build.o
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obj-y += gic.o gic-v2.o
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obj-$(CONFIG_ARM_64) += gic-v3.o
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obj-y += io.o
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obj-y += irq.o
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obj-y += kernel.o
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File diff suppressed because it is too large.
Load diff
@@ -99,6 +99,14 @@ struct arch_domain
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/* Base address for guest GIC */
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paddr_t dbase; /* Distributor base address */
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paddr_t cbase; /* CPU base address */
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#ifdef CONFIG_ARM_64
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/* GIC V3 addressing */
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paddr_t dbase_size; /* Distributor base size */
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paddr_t rbase[MAX_RDIST_COUNT]; /* Re-Distributor base address */
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paddr_t rbase_size[MAX_RDIST_COUNT]; /* Re-Distributor size */
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uint32_t rdist_stride; /* Re-Distributor stride */
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int rdist_count; /* No. of Re-Distributors */
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#endif
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} vgic;
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struct vuart {
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@@ -18,6 +18,10 @@
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#ifndef __ASM_ARM_GIC_H__
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#define __ASM_ARM_GIC_H__
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#define NR_GIC_LOCAL_IRQS NR_LOCAL_IRQS
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#define NR_GIC_SGI 16
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#define MAX_RDIST_COUNT 4
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#define GICD_CTLR (0x000)
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#define GICD_TYPER (0x004)
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#define GICD_IIDR (0x008)
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@@ -154,6 +158,20 @@
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#define DT_MATCH_GIC_V2 DT_MATCH_COMPATIBLE(DT_COMPAT_GIC_CORTEX_A15), \
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DT_MATCH_COMPATIBLE(DT_COMPAT_GIC_CORTEX_A7)
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#define DT_COMPAT_GIC_V3 "arm,gic-v3"
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#define DT_MATCH_GIC_V3 DT_MATCH_COMPATIBLE(DT_COMPAT_GIC_V3)
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/*
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* GICv3 registers that needs to be saved/restored
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*/
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struct gic_v3 {
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uint32_t hcr, vmcr, sre_el1;
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uint32_t apr0[4];
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uint32_t apr1[4];
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uint64_t lr[16];
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};
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/*
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* GICv2 register that needs to be saved/restored
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* on VCPU context switch
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@@ -170,6 +188,7 @@ struct gic_v2 {
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*/
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union gic_state_data {
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struct gic_v2 v2;
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struct gic_v3 v3;
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};
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/*
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@@ -189,6 +208,7 @@ struct gic_lr {
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enum gic_version {
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GIC_V2,
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GIC_V3,
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};
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extern enum gic_version gic_hw_version(void);
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@@ -0,0 +1,154 @@
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/*
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* ARM Generic Interrupt Controller v3 definitions
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*
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* Vijaya Kumar K <vijaya.kumar@caviumnetworks.com>
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* Copyright (c) 2014 Cavium Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __ASM_ARM_GIC_V3_DEFS_H__
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#define __ASM_ARM_GIC_V3_DEFS_H__
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/*
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* Additional registers defined in GIC v3.
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* Common GICD registers are defined in gic.h
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*/
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#define GICD_STATUSR (0x010)
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#define GICD_SETSPI_NSR (0x040)
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#define GICD_CLRSPI_NSR (0x048)
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#define GICD_SETSPI_SR (0x050)
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#define GICD_CLRSPI_SR (0x058)
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#define GICD_IROUTER (0x6000)
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#define GICD_IROUTER31 (0x60F8)
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#define GICD_IROUTER32 (0x6100)
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#define GICD_IROUTERN (0x7FF8)
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#define GICD_PIDR0 (0xFFE0)
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#define GICD_PIDR1 (0xFFE4)
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#define GICD_PIDR2 (0xFFE8)
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#define GICD_PIDR3 (0xFFEC)
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#define GICD_PIDR4 (0xFFD0)
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#define GICD_PIDR5 (0xFFD4)
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#define GICD_PIDR7 (0xFFDC)
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#define GICC_SRE_EL2_SRE (1UL << 0)
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#define GICC_SRE_EL2_DFB (1UL << 1)
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#define GICC_SRE_EL2_DIB (1UL << 2)
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#define GICC_SRE_EL2_ENEL1 (1UL << 3)
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#define GICD_CTLR_RWP (1UL << 31)
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#define GICD_CTLR_ARE_NS (1U << 4)
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#define GICD_CTLR_ENABLE_G1A (1U << 1)
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#define GICD_CTLR_ENABLE_G1 (1U << 0)
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#define GICD_IROUTER_SPI_MODE_ANY (1UL << 31)
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#define GICC_CTLR_EL1_EOImode_drop (1U << 1)
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#define GICR_WAKER_ProcessorSleep (1U << 1)
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#define GICR_WAKER_ChildrenAsleep (1U << 2)
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#define GICD_PIDR2_ARCH_REV_MASK (0xf0)
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#define GICD_PIDR2_ARCH_REV_SHIFT (0x4)
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#define GICD_PIDR2_ARCH_GICV3 (0x3)
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#define GICR_PIDR2_ARCH_REV_MASK GICD_PIDR2_ARCH_REV_MASK
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#define GICR_PIDR2_ARCH_REV_SHIFT GICD_PIDR2_ARCH_REV_SHIFT
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#define GICR_PIDR2_ARCH_GICV3 GICD_PIDR2_ARCH_GICV3
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#define GICR_SYNCR_NOT_BUSY 1
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/*
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* Implementation defined value JEP106?
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* use physical hw value for now
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*/
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#define GICV3_GICD_IIDR_VAL 0x34c
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#define GICV3_GICR_IIDR_VAL GICV3_GICD_IIDR_VAL
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#define GICR_CTLR (0x0000)
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#define GICR_IIDR (0x0004)
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#define GICR_TYPER (0x0008)
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#define GICR_STATUSR (0x0010)
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#define GICR_WAKER (0x0014)
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#define GICR_SETLPIR (0x0040)
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#define GICR_CLRLPIR (0x0048)
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#define GICR_PROPBASER (0x0070)
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#define GICR_PENDBASER (0x0078)
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#define GICR_INVLPIR (0x00A0)
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#define GICR_INVALLR (0x00B0)
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#define GICR_SYNCR (0x00C0)
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#define GICR_MOVLPIR (0x100)
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#define GICR_MOVALLR (0x0110)
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#define GICR_PIDR0 GICD_PIDR0
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#define GICR_PIDR1 GICD_PIDR1
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#define GICR_PIDR2 GICD_PIDR2
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#define GICR_PIDR3 GICD_PIDR3
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#define GICR_PIDR4 GICD_PIDR4
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#define GICR_PIDR5 GICD_PIDR5
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#define GICR_PIDR7 GICD_PIDR7
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/* GICR for SGI's & PPI's */
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#define GICR_IGROUPR0 (0x0080)
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#define GICR_IGRPMODR0 (0x0F80)
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#define GICR_ISENABLER0 (0x0100)
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#define GICR_ICENABLER0 (0x0180)
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#define GICR_ISPENDR0 (0x0200)
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#define GICR_ICPENDR0 (0x0280)
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#define GICR_ISACTIVER0 (0x0300)
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#define GICR_ICACTIVER0 (0x0380)
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#define GICR_IPRIORITYR0 (0x0400)
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#define GICR_IPRIORITYR7 (0x041C)
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#define GICR_ICFGR0 (0x0C00)
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#define GICR_ICFGR1 (0x0C04)
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#define GICR_NSACR (0x0E00)
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#define GICR_TYPER_PLPIS (1U << 0)
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#define GICR_TYPER_VLPIS (1U << 1)
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#define GICR_TYPER_LAST (1U << 4)
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#define DEFAULT_PMR_VALUE 0xff
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#define GICH_VMCR_EOI (1 << 9)
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#define GICH_VMCR_VENG1 (1 << 1)
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#define GICH_LR_VIRTUAL_MASK 0xffff
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#define GICH_LR_VIRTUAL_SHIFT 0
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#define GICH_LR_PHYSICAL_MASK 0x3ff
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#define GICH_LR_PHYSICAL_SHIFT 32
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#define GICH_LR_STATE_MASK 0x3
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#define GICH_LR_STATE_SHIFT 62
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#define GICH_LR_PRIORITY_MASK 0xff
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#define GICH_LR_PRIORITY_SHIFT 48
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#define GICH_LR_HW_MASK 0x1
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#define GICH_LR_HW_SHIFT 61
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#define GICH_LR_GRP_MASK 0x1
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#define GICH_LR_GRP_SHIFT 60
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#define GICH_LR_MAINTENANCE_IRQ (1UL<<41)
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#define GICH_LR_GRP1 (1UL<<60)
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#define GICH_LR_HW (1UL<<61)
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#define GICH_VTR_NRLRGS 0x3f
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#define GICH_VTR_PRIBITS_MASK 0x7
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#define GICH_VTR_PRIBITS_SHIFT 29
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#define GICH_VMCR_PRIORITY_MASK 0xff
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#define GICH_VMCR_PRIORITY_SHIFT 24
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#endif /* __ASM_ARM_GIC_V3_DEFS_H__ */
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/*
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* Local variables:
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* mode: C
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* c-file-style: "BSD"
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* c-basic-offset: 4
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* indent-tabs-mode: nil
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* End:
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*/
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@@ -20,6 +20,19 @@
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#define AFFINITY_MASK(level) ~((_AC(0x1,U) << ((level) * MPIDR_LEVEL_BITS)) - 1)
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/*
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* Macros to extract affinity level. picked from kernel
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*/
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#define MPIDR_LEVEL_BITS_SHIFT 3
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#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
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#define MPIDR_LEVEL_SHIFT(level) \
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(((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT)
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#define MPIDR_AFFINITY_LEVEL(mpidr, level) \
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((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK)
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/* TTBCR Translation Table Base Control Register */
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#define TTBCR_EAE _AC(0x80000000,U)
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#define TTBCR_N_MASK _AC(0x07,U)
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@@ -100,6 +100,59 @@
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#define HSR_SYSREG_CNTP_CTL_EL0 HSR_SYSREG(3,3,c14,c2,1)
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#define HSR_SYSREG_CNTP_TVAL_EL0 HSR_SYSREG(3,3,c14,c2,0)
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/*
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* GIC System register assembly aliases picked from kernel
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*/
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#define ICC_PMR_EL1 S3_0_C4_C6_0
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#define ICC_DIR_EL1 S3_0_C12_C11_1
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#define ICC_SGI1R_EL1 S3_0_C12_C11_5
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#define ICC_EOIR1_EL1 S3_0_C12_C12_1
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#define ICC_IAR1_EL1 S3_0_C12_C12_0
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#define ICC_BPR1_EL1 S3_0_C12_C12_3
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#define ICC_CTLR_EL1 S3_0_C12_C12_4
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#define ICC_SRE_EL1 S3_0_C12_C12_5
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#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
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#define ICH_VSEIR_EL2 S3_4_C12_C9_4
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#define ICC_SRE_EL2 S3_4_C12_C9_5
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#define ICH_HCR_EL2 S3_4_C12_C11_0
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#define ICH_VTR_EL2 S3_4_C12_C11_1
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#define ICH_MISR_EL2 S3_4_C12_C11_2
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#define ICH_EISR_EL2 S3_4_C12_C11_3
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#define ICH_ELSR_EL2 S3_4_C12_C11_5
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#define ICH_VMCR_EL2 S3_4_C12_C11_7
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#define __LR0_EL2(x) S3_4_C12_C12_ ## x
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#define __LR8_EL2(x) S3_4_C12_C13_ ## x
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#define ICH_LR0_EL2 __LR0_EL2(0)
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#define ICH_LR1_EL2 __LR0_EL2(1)
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#define ICH_LR2_EL2 __LR0_EL2(2)
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#define ICH_LR3_EL2 __LR0_EL2(3)
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#define ICH_LR4_EL2 __LR0_EL2(4)
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#define ICH_LR5_EL2 __LR0_EL2(5)
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#define ICH_LR6_EL2 __LR0_EL2(6)
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#define ICH_LR7_EL2 __LR0_EL2(7)
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#define ICH_LR8_EL2 __LR8_EL2(0)
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#define ICH_LR9_EL2 __LR8_EL2(1)
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#define ICH_LR10_EL2 __LR8_EL2(2)
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#define ICH_LR11_EL2 __LR8_EL2(3)
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#define ICH_LR12_EL2 __LR8_EL2(4)
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#define ICH_LR13_EL2 __LR8_EL2(5)
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#define ICH_LR14_EL2 __LR8_EL2(6)
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#define ICH_LR15_EL2 __LR8_EL2(7)
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#define __AP0Rx_EL2(x) S3_4_C12_C8_ ## x
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#define ICH_AP0R0_EL2 __AP0Rx_EL2(0)
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#define ICH_AP0R1_EL2 __AP0Rx_EL2(1)
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#define ICH_AP0R2_EL2 __AP0Rx_EL2(2)
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#define ICH_AP0R3_EL2 __AP0Rx_EL2(3)
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#define __AP1Rx_EL2(x) S3_4_C12_C9_ ## x
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#define ICH_AP1R0_EL2 __AP1Rx_EL2(0)
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#define ICH_AP1R1_EL2 __AP1Rx_EL2(1)
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#define ICH_AP1R2_EL2 __AP1Rx_EL2(2)
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#define ICH_AP1R3_EL2 __AP1Rx_EL2(3)
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#endif
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