diff --git a/xen/arch/x86/pv/traps.c b/xen/arch/x86/pv/traps.c
index c3c0976c44..26a468108a 100644
--- a/xen/arch/x86/pv/traps.c
+++ b/xen/arch/x86/pv/traps.c
@@ -99,7 +99,7 @@ void pv_inject_event(const struct x86_event *event)
  * Called from asm to set up the MCE trapbounce info.
  * Returns false no callback is set up, else true.
  */
-bool set_guest_machinecheck_trapbounce(void)
+bool asmlinkage set_guest_machinecheck_trapbounce(void)
 {
     struct vcpu *curr = current;
     struct trap_bounce *tb = &curr->arch.pv.trap_bounce;
@@ -114,7 +114,7 @@ bool set_guest_machinecheck_trapbounce(void)
  * Called from asm to set up the NMI trapbounce info.
  * Returns false if no callback is set up, else true.
  */
-bool set_guest_nmi_trapbounce(void)
+bool asmlinkage set_guest_nmi_trapbounce(void)
 {
     struct vcpu *curr = current;
     struct trap_bounce *tb = &curr->arch.pv.trap_bounce;
diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c
index 44da5efa1d..27c63d1d97 100644
--- a/xen/arch/x86/setup.c
+++ b/xen/arch/x86/setup.c
@@ -877,6 +877,8 @@ static void noreturn init_done(void)
     startup_cpu_idle_loop();
 }
 
+unsigned int xen_msr_s_cet_value(void); /* To avoid ifdefary, and placate MISRA */
+
 #if defined(CONFIG_XEN_SHSTK) || defined(CONFIG_XEN_IBT)
 /*
  * Used by AP and S3 asm code to calcualte the appropriate MSR_S_CET setting.
@@ -888,8 +890,6 @@ unsigned int xen_msr_s_cet_value(void)
     return ((cpu_has_xen_shstk ? CET_SHSTK_EN | CET_WRSS_EN : 0) |
             (cpu_has_xen_ibt   ? CET_ENDBR_EN : 0));
 }
-#else
-unsigned int xen_msr_s_cet_value(void); /* To avoid ifdefary */
 #endif
 
 /* Reinitalise all state referring to the old virtual address of the stack. */