diff --git a/docs/misc/xen-command-line.markdown b/docs/misc/xen-command-line.markdown index 4c8fe2f25f..450b222734 100644 --- a/docs/misc/xen-command-line.markdown +++ b/docs/misc/xen-command-line.markdown @@ -1172,6 +1172,15 @@ based interrupts. Any higher IRQs will be available for use via PCI MSI. ### maxcpus > `= ` +### max\_lpi\_bits +> `= ` + +Specifies the number of ARM GICv3 LPI interrupts to allocate on the host, +presented as the number of bits needed to encode it. This must be at least +14 and not exceed 32, and each LPI requires one byte (configuration) and +one pending bit to be allocated. +Defaults to 20 bits (to cover at most 1048576 interrupts). + ### mce > `= ` diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile index 39c0a03685..6be85ab5c4 100644 --- a/xen/arch/arm/Makefile +++ b/xen/arch/arm/Makefile @@ -19,6 +19,7 @@ obj-y += gic.o obj-y += gic-v2.o obj-$(CONFIG_HAS_GICV3) += gic-v3.o obj-$(CONFIG_HAS_ITS) += gic-v3-its.o +obj-$(CONFIG_HAS_ITS) += gic-v3-lpi.o obj-y += guestcopy.o obj-y += hvm.o obj-y += io.o diff --git a/xen/arch/arm/gic-v3-lpi.c b/xen/arch/arm/gic-v3-lpi.c new file mode 100644 index 0000000000..27e9bf5963 --- /dev/null +++ b/xen/arch/arm/gic-v3-lpi.c @@ -0,0 +1,227 @@ +/* + * xen/arch/arm/gic-v3-lpi.c + * + * ARM GICv3 Locality-specific Peripheral Interrupts (LPI) support + * + * Copyright (C) 2016,2017 - ARM Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; under version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LPI_PROPTABLE_NEEDS_FLUSHING (1U << 0) + +/* Global state */ +static struct { + /* The global LPI property table, shared by all redistributors. */ + uint8_t *lpi_property; + /* + * Number of physical LPIs the host supports. This is a property of + * the GIC hardware. We depart from the habit of naming these things + * "physical" in Xen, as the GICv3/4 spec uses the term "physical LPI" + * in a different context to differentiate them from "virtual LPIs". + */ + unsigned long int max_host_lpi_ids; + unsigned int flags; +} lpi_data; + +struct lpi_redist_data { + void *pending_table; +}; + +static DEFINE_PER_CPU(struct lpi_redist_data, lpi_redist); + +#define MAX_NR_HOST_LPIS (lpi_data.max_host_lpi_ids - LPI_OFFSET) + +static int gicv3_lpi_allocate_pendtable(uint64_t *reg) +{ + uint64_t val; + void *pendtable; + + if ( this_cpu(lpi_redist).pending_table ) + return -EBUSY; + + val = GIC_BASER_CACHE_RaWaWb << GICR_PENDBASER_INNER_CACHEABILITY_SHIFT; + val |= GIC_BASER_CACHE_SameAsInner << GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT; + val |= GIC_BASER_InnerShareable << GICR_PENDBASER_SHAREABILITY_SHIFT; + + /* + * The pending table holds one bit per LPI and even covers bits for + * interrupt IDs below 8192, so we allocate the full range. + * The GICv3 imposes a 64KB alignment requirement, also requires + * physically contiguous memory. + */ + pendtable = _xzalloc(lpi_data.max_host_lpi_ids / 8, SZ_64K); + if ( !pendtable ) + return -ENOMEM; + + /* Make sure the physical address can be encoded in the register. */ + if ( virt_to_maddr(pendtable) & ~GENMASK(51, 16) ) + { + xfree(pendtable); + return -ERANGE; + } + clean_and_invalidate_dcache_va_range(pendtable, + lpi_data.max_host_lpi_ids / 8); + + this_cpu(lpi_redist).pending_table = pendtable; + + val |= GICR_PENDBASER_PTZ; + + val |= virt_to_maddr(pendtable); + + *reg = val; + + return 0; +} + +/* + * Tell a redistributor about the (shared) property table, allocating one + * if not already done. + */ +static int gicv3_lpi_set_proptable(void __iomem * rdist_base) +{ + uint64_t reg; + + reg = GIC_BASER_CACHE_RaWaWb << GICR_PROPBASER_INNER_CACHEABILITY_SHIFT; + reg |= GIC_BASER_CACHE_SameAsInner << GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT; + reg |= GIC_BASER_InnerShareable << GICR_PROPBASER_SHAREABILITY_SHIFT; + + /* + * The property table is shared across all redistributors, so allocate + * this only once, but return the same value on subsequent calls. + */ + if ( !lpi_data.lpi_property ) + { + /* The property table holds one byte per LPI. */ + void *table = _xmalloc(lpi_data.max_host_lpi_ids, SZ_4K); + + if ( !table ) + return -ENOMEM; + + /* Make sure the physical address can be encoded in the register. */ + if ( (virt_to_maddr(table) & ~GENMASK(51, 12)) ) + { + xfree(table); + return -ERANGE; + } + memset(table, GIC_PRI_IRQ | LPI_PROP_RES1, MAX_NR_HOST_LPIS); + clean_and_invalidate_dcache_va_range(table, MAX_NR_HOST_LPIS); + lpi_data.lpi_property = table; + } + + /* Encode the number of bits needed, minus one */ + reg |= fls(lpi_data.max_host_lpi_ids - 1) - 1; + + reg |= virt_to_maddr(lpi_data.lpi_property); + + writeq_relaxed(reg, rdist_base + GICR_PROPBASER); + reg = readq_relaxed(rdist_base + GICR_PROPBASER); + + /* If we can't do shareable, we have to drop cacheability as well. */ + if ( !(reg & GICR_PROPBASER_SHAREABILITY_MASK) ) + { + reg &= ~GICR_PROPBASER_INNER_CACHEABILITY_MASK; + reg |= GIC_BASER_CACHE_nC << GICR_PROPBASER_INNER_CACHEABILITY_SHIFT; + } + + /* Remember that we have to flush the property table if non-cacheable. */ + if ( (reg & GICR_PROPBASER_INNER_CACHEABILITY_MASK) <= GIC_BASER_CACHE_nC ) + { + lpi_data.flags |= LPI_PROPTABLE_NEEDS_FLUSHING; + /* Update the redistributors knowledge about the attributes. */ + writeq_relaxed(reg, rdist_base + GICR_PROPBASER); + } + + return 0; +} + +int gicv3_lpi_init_rdist(void __iomem * rdist_base) +{ + uint32_t reg; + uint64_t table_reg; + int ret; + + /* We don't support LPIs without an ITS. */ + if ( !gicv3_its_host_has_its() ) + return -ENODEV; + + /* Make sure LPIs are disabled before setting up the tables. */ + reg = readl_relaxed(rdist_base + GICR_CTLR); + if ( reg & GICR_CTLR_ENABLE_LPIS ) + return -EBUSY; + + ret = gicv3_lpi_allocate_pendtable(&table_reg); + if ( ret ) + return ret; + writeq_relaxed(table_reg, rdist_base + GICR_PENDBASER); + table_reg = readq_relaxed(rdist_base + GICR_PENDBASER); + + /* If the hardware reports non-shareable, drop cacheability as well. */ + if ( !(table_reg & GICR_PENDBASER_SHAREABILITY_MASK) ) + { + table_reg &= GICR_PENDBASER_SHAREABILITY_MASK; + table_reg &= GICR_PENDBASER_INNER_CACHEABILITY_MASK; + table_reg |= GIC_BASER_CACHE_nC << GICR_PENDBASER_INNER_CACHEABILITY_SHIFT; + + writeq_relaxed(table_reg, rdist_base + GICR_PENDBASER); + } + + return gicv3_lpi_set_proptable(rdist_base); +} + +static unsigned int max_lpi_bits = 20; +integer_param("max_lpi_bits", max_lpi_bits); + +int gicv3_lpi_init_host_lpis(unsigned int host_lpi_bits) +{ + /* + * An implementation needs to support at least 14 bits of LPI IDs. + * Tell the user about it, the actual number is reported below. + */ + if ( max_lpi_bits < 14 || max_lpi_bits > 32 ) + printk(XENLOG_WARNING "WARNING: max_lpi_bits must be between 14 and 32, adjusting.\n"); + + max_lpi_bits = max(max_lpi_bits, 14U); + lpi_data.max_host_lpi_ids = BIT(min(host_lpi_bits, max_lpi_bits)); + + /* + * Warn if the number of LPIs are quite high, as the user might not want + * to waste megabytes of memory for a mostly empty table. + * It's very unlikely that we need more than 24 bits worth of LPIs. + */ + if ( lpi_data.max_host_lpi_ids > BIT(24) ) + warning_add("Using high number of LPIs, limit memory usage with max_lpi_bits\n"); + + printk("GICv3: using at most %lu LPIs on the host.\n", MAX_NR_HOST_LPIS); + + return 0; +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index d3d5784ac3..54d2235ee7 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -547,6 +547,9 @@ static void __init gicv3_dist_init(void) type = readl_relaxed(GICD + GICD_TYPER); nr_lines = 32 * ((type & GICD_TYPE_LINES) + 1); + if ( type & GICD_TYPE_LPIS ) + gicv3_lpi_init_host_lpis(GICD_TYPE_ID_BITS(type)); + printk("GICv3: %d lines, (IID %8.8x).\n", nr_lines, readl_relaxed(GICD + GICD_IIDR)); @@ -659,6 +662,20 @@ static int __init gicv3_populate_rdist(void) if ( (typer >> 32) == aff ) { this_cpu(rbase) = ptr; + + if ( typer & GICR_TYPER_PLPIS ) + { + int ret; + + ret = gicv3_lpi_init_rdist(ptr); + if ( ret && ret != -ENODEV ) + { + printk("GICv3: CPU%d: Cannot initialize LPIs: %u\n", + smp_processor_id(), ret); + break; + } + } + printk("GICv3: CPU%d: Found redistributor in region %d @%p\n", smp_processor_id(), i, ptr); return 0; diff --git a/xen/include/asm-arm/gic_v3_defs.h b/xen/include/asm-arm/gic_v3_defs.h index 6bd25a54a2..2792ffdb86 100644 --- a/xen/include/asm-arm/gic_v3_defs.h +++ b/xen/include/asm-arm/gic_v3_defs.h @@ -45,6 +45,9 @@ /* Additional bits in GICD_TYPER defined by GICv3 */ #define GICD_TYPE_ID_BITS_SHIFT 19 +#define GICD_TYPE_ID_BITS(r) ((((r) >> GICD_TYPE_ID_BITS_SHIFT) & 0x1f) + 1) + +#define GICD_TYPE_LPIS (1U << 17) #define GICD_CTLR_RWP (1UL << 31) #define GICD_CTLR_ARE_NS (1U << 4) @@ -95,12 +98,61 @@ #define GICR_IGRPMODR0 (0x0D00) #define GICR_NSACR (0x0E00) +#define GICR_CTLR_ENABLE_LPIS (1U << 0) + #define GICR_TYPER_PLPIS (1U << 0) #define GICR_TYPER_VLPIS (1U << 1) #define GICR_TYPER_LAST (1U << 4) +/* For specifying the inner cacheability type only */ +#define GIC_BASER_CACHE_nCnB 0ULL +/* For specifying the outer cacheability type only */ +#define GIC_BASER_CACHE_SameAsInner 0ULL +#define GIC_BASER_CACHE_nC 1ULL +#define GIC_BASER_CACHE_RaWt 2ULL +#define GIC_BASER_CACHE_RaWb 3ULL +#define GIC_BASER_CACHE_WaWt 4ULL +#define GIC_BASER_CACHE_WaWb 5ULL +#define GIC_BASER_CACHE_RaWaWt 6ULL +#define GIC_BASER_CACHE_RaWaWb 7ULL +#define GIC_BASER_CACHE_MASK 7ULL + +#define GIC_BASER_NonShareable 0ULL +#define GIC_BASER_InnerShareable 1ULL +#define GIC_BASER_OuterShareable 2ULL + +#define GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT 56 +#define GICR_PROPBASER_OUTER_CACHEABILITY_MASK \ + (7UL << GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT) +#define GICR_PROPBASER_SHAREABILITY_SHIFT 10 +#define GICR_PROPBASER_SHAREABILITY_MASK \ + (3UL << GICR_PROPBASER_SHAREABILITY_SHIFT) +#define GICR_PROPBASER_INNER_CACHEABILITY_SHIFT 7 +#define GICR_PROPBASER_INNER_CACHEABILITY_MASK \ + (7UL << GICR_PROPBASER_INNER_CACHEABILITY_SHIFT) +#define GICR_PROPBASER_RES0_MASK \ + (GENMASK(63, 59) | GENMASK(55, 52) | GENMASK(6, 5)) + +#define GICR_PENDBASER_SHAREABILITY_SHIFT 10 +#define GICR_PENDBASER_INNER_CACHEABILITY_SHIFT 7 +#define GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT 56 +#define GICR_PENDBASER_SHAREABILITY_MASK \ + (3UL << GICR_PENDBASER_SHAREABILITY_SHIFT) +#define GICR_PENDBASER_INNER_CACHEABILITY_MASK \ + (7UL << GICR_PENDBASER_INNER_CACHEABILITY_SHIFT) +#define GICR_PENDBASER_OUTER_CACHEABILITY_MASK \ + (7UL << GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT) +#define GICR_PENDBASER_PTZ BIT(62) +#define GICR_PENDBASER_RES0_MASK \ + (BIT(63) | GENMASK(61, 59) | GENMASK(55, 52) | \ + GENMASK(15, 12) | GENMASK(6, 0)) + #define DEFAULT_PMR_VALUE 0xff +#define LPI_PROP_PRIO_MASK 0xfc +#define LPI_PROP_RES1 (1 << 1) +#define LPI_PROP_ENABLED (1 << 0) + #define GICH_VMCR_EOI (1 << 9) #define GICH_VMCR_VENG1 (1 << 1) diff --git a/xen/include/asm-arm/gic_v3_its.h b/xen/include/asm-arm/gic_v3_its.h index 880904d1d6..d1382c11a0 100644 --- a/xen/include/asm-arm/gic_v3_its.h +++ b/xen/include/asm-arm/gic_v3_its.h @@ -76,7 +76,10 @@ void gicv3_its_dt_init(const struct dt_device_node *node); bool gicv3_its_host_has_its(void); -/* Initialize the host structures for the host ITSes. */ +int gicv3_lpi_init_rdist(void __iomem * rdist_base); + +/* Initialize the host structures for LPIs and the host ITSes. */ +int gicv3_lpi_init_host_lpis(unsigned int host_lpi_bits); int gicv3_its_init(void); #else @@ -90,6 +93,16 @@ static inline bool gicv3_its_host_has_its(void) return false; } +static inline int gicv3_lpi_init_rdist(void __iomem * rdist_base) +{ + return -ENODEV; +} + +static inline int gicv3_lpi_init_host_lpis(unsigned int host_lpi_bits) +{ + return 0; +} + static inline int gicv3_its_init(void) { return 0; diff --git a/xen/include/asm-arm/irq.h b/xen/include/asm-arm/irq.h index 4849f16ea0..f940092045 100644 --- a/xen/include/asm-arm/irq.h +++ b/xen/include/asm-arm/irq.h @@ -18,8 +18,16 @@ struct arch_irq_desc { }; #define NR_LOCAL_IRQS 32 + +/* + * This only covers the interrupts that Xen cares about, so SGIs, PPIs and + * SPIs. LPIs are too numerous, also only propagated to guests, so they are + * not included in this number. + */ #define NR_IRQS 1024 +#define LPI_OFFSET 8192 + #define nr_irqs NR_IRQS #define nr_static_irqs NR_IRQS #define arch_hwdom_irqs(domid) NR_IRQS