x86, hvm: Expose host core/HT topology to HVM guests.

Based on an initial patch by Nitin Kamble <nitin.a.kamble@intel.com>
Signed-off-by: Keir Fraser <keir.fraser@citrix.com>

tools/libxc/xc_cpuid_x86.c

@@ -92,6 +92,7 @@ static void amd_xc_cpuid_policy(
 
         /* Filter all other features according to a whitelist. */
         regs[2] &= ((is_64bit ? bitmaskof(X86_FEATURE_LAHF_LM) : 0) |
+                    bitmaskof(X86_FEATURE_CMP_LEGACY) |
                     bitmaskof(X86_FEATURE_ALTMOVCR) |
                     bitmaskof(X86_FEATURE_ABM) |
                     bitmaskof(X86_FEATURE_SSE4A) |
@@ -108,6 +109,14 @@ static void amd_xc_cpuid_policy(
                     bitmaskof(X86_FEATURE_3DNOWEXT));
         break;
     }
+
+    case 0x80000008:
+        /*
+         * ECX[15:12] is ApicIdCoreSize: ECX[7:0] is NumberOfCores (minus one).
+         * Update to reflect vLAPIC_ID = vCPU_ID * 2.
+         */
+        regs[2] = ((regs[2] & 0xf000u) + 1) | ((regs[2] & 0xffu) << 1) | 1u;
+        break;
     }
 }
 
@@ -123,8 +132,13 @@ static void intel_xc_cpuid_policy(
         break;
 
     case 0x00000004:
-        regs[0] &= 0x3FF;
-        regs[3] &= 0x3FF;
+        /*
+         * EAX[31:26] is Maximum Cores Per Package (minus one).
+         * Update to reflect vLAPIC_ID = vCPU_ID * 2.
+         */
+        regs[0] = (((regs[0] & 0x7c000000u) << 1) | 0x04000000u |
+                   (regs[0] & 0x3ffu));
+        regs[3] &= 0x3ffu;
         break;
 
     case 0x80000001: {
@@ -141,6 +155,11 @@ static void intel_xc_cpuid_policy(
     case 0x80000005:
         regs[0] = regs[1] = regs[2] = 0;
         break;
+
+    case 0x80000008:
+        /* Mask AMD Number of Cores information. */
+        regs[2] = 0;
+        break;
     }
 }
 
@@ -162,6 +181,12 @@ static void xc_cpuid_hvm_policy(
         break;
 
     case 0x00000001:
+        /*
+         * EBX[23:16] is Maximum Logical Processors Per Package.
+         * Update to reflect vLAPIC_ID = vCPU_ID * 2.
+         */
+        regs[1] = (regs[1] & 0x0000ffffu) | ((regs[1] & 0x007f0000u) << 1);
+
         regs[2] &= (bitmaskof(X86_FEATURE_XMM3) |
                     bitmaskof(X86_FEATURE_SSSE3) |
                     bitmaskof(X86_FEATURE_CX16) |
@@ -189,7 +214,8 @@ static void xc_cpuid_hvm_policy(
                     bitmaskof(X86_FEATURE_MMX) |
                     bitmaskof(X86_FEATURE_FXSR) |
                     bitmaskof(X86_FEATURE_XMM) |
-                    bitmaskof(X86_FEATURE_XMM2));
+                    bitmaskof(X86_FEATURE_XMM2) |
+                    bitmaskof(X86_FEATURE_HT));
             
         /* We always support MTRR MSRs. */
         regs[3] |= bitmaskof(X86_FEATURE_MTRR);
@@ -211,7 +237,7 @@ static void xc_cpuid_hvm_policy(
 
     case 0x80000008:
         regs[0] &= 0x0000ffffu;
-        regs[1] = regs[2] = regs[3] = 0;
+        regs[1] = regs[3] = 0;
         break;
 
     case 0x00000002: /* Intel cache info (dumped by AMD policy) */