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Intel vt-d specific changes in arch/x86/hvm/vmx/vtd.

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Signed-off-by: Allen Kay <allen.m.kay@intel.com>
Signed-off-by: Guy Zana <guy@neocleus.com>
This commit is contained in:
kfraser@localhost.localdomain committed 2007-09-14 16:40:49 +01:00
1 parent 9e6ca368e2
commit ccfe4e0845
9 files changed
+3562
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xen/arch/x86/hvm/vmx/vtd/Makefile
+4
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@@ -0,0 +1,4 @@
obj-y += intel-iommu.o
obj-y += dmar.o
obj-y += utils.o
obj-y += io.o
xen/arch/x86/hvm/vmx/vtd/dmar.c
+494
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@@ -0,0 +1,494 @@
/*
* Copyright (c) 2006, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
* Place - Suite 330, Boston, MA 02111-1307 USA.
*
* Copyright (C) Ashok Raj <ashok.raj@intel.com>
* Copyright (C) Shaohua Li <shaohua.li@intel.com>
* Copyright (C) Allen Kay <allen.m.kay@intel.com> - adapted to xen
*/
#include <xen/init.h>
#include <xen/bitmap.h>
#include <xen/kernel.h>
#include <xen/acpi.h>
#include <xen/mm.h>
#include <xen/xmalloc.h>
#include <asm/string.h>
#include "dmar.h"
#include "pci-direct.h"
#include "pci_regs.h"
#undef PREFIX
#define PREFIX VTDPREFIX "ACPI DMAR:"
#define DEBUG
#define MIN_SCOPE_LEN (sizeof(struct acpi_pci_path) + sizeof(struct acpi_dev_scope))
LIST_HEAD(acpi_drhd_units);
LIST_HEAD(acpi_rmrr_units);
LIST_HEAD(acpi_atsr_units);
LIST_HEAD(acpi_ioapic_units);
u8 dmar_host_address_width;
static int __init acpi_register_drhd_unit(struct acpi_drhd_unit *drhd)
{
/*
* add INCLUDE_ALL at the tail, so scan the list will find it at
* the very end.
*/
if (drhd->include_all)
list_add_tail(&drhd->list, &acpi_drhd_units);
else
list_add(&drhd->list, &acpi_drhd_units);
return 0;
}
static int __init acpi_register_rmrr_unit(struct acpi_rmrr_unit *rmrr)
{
list_add(&rmrr->list, &acpi_rmrr_units);
return 0;
}
static int acpi_pci_device_match(struct pci_dev *devices, int cnt,
struct pci_dev *dev)
{
int i;
for (i = 0; i < cnt; i++) {
if ((dev->bus == devices->bus) &&
(dev->devfn == devices->devfn))
return 1;
devices++;
}
return 0;
}
static int __init acpi_register_atsr_unit(struct acpi_atsr_unit *atsr)
{
/*
* add ALL_PORTS at the tail, so scan the list will find it at
* the very end.
*/
if (atsr->all_ports)
list_add_tail(&atsr->list, &acpi_atsr_units);
else
list_add(&atsr->list, &acpi_atsr_units);
return 0;
}
struct acpi_drhd_unit * acpi_find_matched_drhd_unit(struct pci_dev *dev)
{
struct acpi_drhd_unit *drhd;
struct acpi_drhd_unit *include_all_drhd;
include_all_drhd = NULL;
list_for_each_entry(drhd, &acpi_drhd_units, list) {
if (drhd->include_all)
include_all_drhd = drhd;
if (acpi_pci_device_match(drhd->devices,
drhd->devices_cnt, dev))
{
gdprintk(XENLOG_INFO VTDPREFIX,
"acpi_find_matched_drhd_unit: drhd->address = %lx\n",
drhd->address);
return drhd;
}
}
if (include_all_drhd) {
gdprintk(XENLOG_INFO VTDPREFIX,
"acpi_find_matched_drhd_unit:include_all_drhd->addr = %lx\n",
include_all_drhd->address);
return include_all_drhd;;
}
return(NULL);
}
struct acpi_rmrr_unit * acpi_find_matched_rmrr_unit(struct pci_dev *dev)
{
struct acpi_rmrr_unit *rmrr;
list_for_each_entry(rmrr, &acpi_rmrr_units, list) {
if (acpi_pci_device_match(rmrr->devices,
rmrr->devices_cnt, dev))
goto out;
}
rmrr = NULL;
out:
return rmrr;
}
struct acpi_atsr_unit * acpi_find_matched_atsr_unit(struct pci_dev *dev)
{
struct acpi_atsr_unit *atsru;
struct acpi_atsr_unit *all_ports_atsru;
all_ports_atsru = NULL;
list_for_each_entry(atsru, &acpi_atsr_units, list) {
if (atsru->all_ports)
all_ports_atsru = atsru;
if (acpi_pci_device_match(atsru->devices, atsru->devices_cnt, dev))
return atsru;
}
if (all_ports_atsru) {
gdprintk(XENLOG_INFO VTDPREFIX,
"acpi_find_matched_atsr_unit: all_ports_atsru\n");
return all_ports_atsru;;
}
return(NULL);
}
static int __init acpi_parse_dev_scope(void *start, void *end, int *cnt,
struct pci_dev **devices)
{
struct acpi_dev_scope *scope;
u8 bus, sub_bus, sec_bus;
struct acpi_pci_path *path;
struct acpi_ioapic_unit *acpi_ioapic_unit = NULL;
int count, dev_count=0;
struct pci_dev *pdev;
u8 dev, func;
u32 l;
void *tmp;
*cnt = 0;
tmp = start;
while (start < end) {
scope = start;
if (scope->length < MIN_SCOPE_LEN ||
(scope->dev_type != ACPI_DEV_ENDPOINT &&
scope->dev_type != ACPI_DEV_P2PBRIDGE)) {
printk(KERN_WARNING PREFIX "Invalid device scope\n");
return -EINVAL;
}
(*cnt)++;
start += scope->length;
}
start = tmp;
while (start < end) {
scope = start;
path = (struct acpi_pci_path *)(scope + 1);
count = (scope->length - sizeof(struct acpi_dev_scope))
/sizeof(struct acpi_pci_path);
bus = scope->start_bus;
while (--count) {
bus = read_pci_config_byte(bus, path->dev,
path->fn, PCI_SECONDARY_BUS);
path++;
}
if (scope->dev_type == ACPI_DEV_ENDPOINT) {
printk(KERN_WARNING PREFIX
"found endpoint: bdf = %x:%x:%x\n", bus, path->dev, path->fn);
dev_count++;
} else if (scope->dev_type == ACPI_DEV_P2PBRIDGE) {
printk(KERN_WARNING PREFIX
"found bridge: bdf = %x:%x:%x\n", bus, path->dev, path->fn);
sec_bus = read_pci_config_byte(bus, path->dev,
path->fn, PCI_SECONDARY_BUS);
sub_bus = read_pci_config_byte(bus, path->dev,
path->fn, PCI_SUBORDINATE_BUS);
while (sec_bus <= sub_bus) {
for (dev = 0; dev < 32; dev++) {
for (func = 0; func < 8; func++) {
l = read_pci_config(sec_bus, dev, func, PCI_VENDOR_ID);
/* some broken boards return 0 or ~0 if a slot is empty: */
if (l == 0xffffffff || l == 0x00000000 ||
l == 0x0000ffff || l == 0xffff0000)
break;
dev_count++;
}
}
sec_bus++;
}
} else if (scope->dev_type == ACPI_DEV_IOAPIC) {
printk(KERN_WARNING PREFIX
"found IOAPIC: bdf = %x:%x:%x\n", bus, path->dev, path->fn);
dev_count++;
} else {
printk(KERN_WARNING PREFIX
"found MSI HPET: bdf = %x:%x:%x\n", bus, path->dev, path->fn);
dev_count++;
}
start += scope->length;
}
*cnt = dev_count;
*devices = xmalloc_array(struct pci_dev, *cnt);
if (!*devices)
return -ENOMEM;
memset(*devices, 0, sizeof(struct pci_dev) * (*cnt));
pdev = *devices;
start = tmp;
while (start < end) {
scope = start;
path = (struct acpi_pci_path *)(scope + 1);
count = (scope->length - sizeof(struct acpi_dev_scope))
/sizeof(struct acpi_pci_path);
bus = scope->start_bus;
while (--count) {
bus = read_pci_config_byte(bus, path->dev, path->fn, PCI_SECONDARY_BUS);
path++;
}
if (scope->dev_type == ACPI_DEV_ENDPOINT) {
printk(KERN_WARNING PREFIX
"found endpoint: bdf = %x:%x:%x\n", bus, path->dev, path->fn);
pdev->bus = bus;
pdev->devfn = PCI_DEVFN(path->dev, path->fn);
pdev++;
} else if (scope->dev_type == ACPI_DEV_P2PBRIDGE) {
printk(KERN_WARNING PREFIX
"found bridge: bus = %x dev = %x func = %x\n", bus, path->dev, path->fn);
sec_bus = read_pci_config_byte(bus, path->dev, path->fn, PCI_SECONDARY_BUS);
sub_bus = read_pci_config_byte(bus, path->dev, path->fn, PCI_SUBORDINATE_BUS);
while (sec_bus <= sub_bus) {
for (dev = 0; dev < 32; dev++) {
for (func = 0; func < 8; func++) {
l = read_pci_config(sec_bus, dev, func, PCI_VENDOR_ID);
/* some broken boards return 0 or ~0 if a slot is empty: */
if (l == 0xffffffff || l == 0x00000000 ||
l == 0x0000ffff || l == 0xffff0000)
break;
pdev->bus = sec_bus;
pdev->devfn = PCI_DEVFN(dev, func);
pdev++;
}
}
sec_bus++;
}
} else if (scope->dev_type == ACPI_DEV_IOAPIC) {
acpi_ioapic_unit = xmalloc(struct acpi_ioapic_unit);
acpi_ioapic_unit->apic_id = scope->enum_id;
acpi_ioapic_unit->ioapic.bdf.bus = bus;
acpi_ioapic_unit->ioapic.bdf.dev = path->dev;
acpi_ioapic_unit->ioapic.bdf.func = path->fn;
list_add(&acpi_ioapic_unit->list, &acpi_ioapic_units);
printk(KERN_WARNING PREFIX
"found IOAPIC: bus = %x dev = %x func = %x\n", bus, path->dev, path->fn);
} else {
printk(KERN_WARNING PREFIX
"found MSI HPET: bus = %x dev = %x func = %x\n", bus, path->dev, path->fn);
}
start += scope->length;
}
return 0;
}
static int __init
acpi_parse_one_drhd(struct acpi_dmar_entry_header *header)
{
struct acpi_table_drhd * drhd = (struct acpi_table_drhd *)header;
struct acpi_drhd_unit *dmaru;
int ret = 0;
static int include_all;
dmaru = xmalloc(struct acpi_drhd_unit);
if (!dmaru)
return -ENOMEM;
memset(dmaru, 0, sizeof(struct acpi_drhd_unit));
dmaru->address = drhd->address;
dmaru->include_all = drhd->flags & 1; /* BIT0: INCLUDE_ALL */
printk(KERN_WARNING PREFIX "dmaru->address = %lx\n", dmaru->address);
if (!dmaru->include_all) {
ret = acpi_parse_dev_scope((void *)(drhd + 1),
((void *)drhd) + header->length,
&dmaru->devices_cnt, &dmaru->devices);
}
else {
printk(KERN_WARNING PREFIX "found INCLUDE_ALL\n");
/* Only allow one INCLUDE_ALL */
if (include_all) {
printk(KERN_WARNING PREFIX "Only one INCLUDE_ALL "
"device scope is allowed\n");
ret = -EINVAL;
}
include_all = 1;
}
if (ret)
xfree(dmaru);
else
acpi_register_drhd_unit(dmaru);
return ret;
}
static int __init
acpi_parse_one_rmrr(struct acpi_dmar_entry_header *header)
{
struct acpi_table_rmrr *rmrr = (struct acpi_table_rmrr *)header;
struct acpi_rmrr_unit *rmrru;
int ret = 0;
rmrru = xmalloc(struct acpi_rmrr_unit);
if (!rmrru)
return -ENOMEM;
memset(rmrru, 0, sizeof(struct acpi_rmrr_unit));
#ifdef VTD_DEBUG
gdprintk(XENLOG_INFO VTDPREFIX,
"acpi_parse_one_rmrr: base = %lx end = %lx\n",
rmrr->base_address, rmrr->end_address);
#endif
rmrru->base_address = rmrr->base_address;
rmrru->end_address = rmrr->end_address;
ret = acpi_parse_dev_scope((void *)(rmrr + 1),
((void*)rmrr) + header->length,
&rmrru->devices_cnt, &rmrru->devices);
if (ret || (rmrru->devices_cnt == 0))
xfree(rmrru);
else
acpi_register_rmrr_unit(rmrru);
return ret;
}
static int __init
acpi_parse_one_atsr(struct acpi_dmar_entry_header *header)
{
struct acpi_table_atsr *atsr = (struct acpi_table_atsr *)header;
struct acpi_atsr_unit *atsru;
int ret = 0;
static int all_ports;
atsru = xmalloc(struct acpi_atsr_unit);
if (!atsru)
return -ENOMEM;
memset(atsru, 0, sizeof(struct acpi_atsr_unit));
atsru->all_ports = atsr->flags & 1; /* BIT0: ALL_PORTS */
if (!atsru->all_ports) {
ret = acpi_parse_dev_scope((void *)(atsr + 1),
((void *)atsr) + header->length,
&atsru->devices_cnt, &atsru->devices);
}
else {
printk(KERN_WARNING PREFIX "found ALL_PORTS\n");
/* Only allow one ALL_PORTS */
if (all_ports) {
printk(KERN_WARNING PREFIX "Only one ALL_PORTS "
"device scope is allowed\n");
ret = -EINVAL;
}
all_ports = 1;
}
if (ret)
xfree(atsr);
else
acpi_register_atsr_unit(atsru);
return ret;
}
static void __init
acpi_table_print_dmar_entry(struct acpi_dmar_entry_header *header)
{
struct acpi_table_drhd *drhd;
struct acpi_table_rmrr *rmrr;
switch (header->type) {
case ACPI_DMAR_DRHD:
drhd = (struct acpi_table_drhd *)header;
break;
case ACPI_DMAR_RMRR:
rmrr = (struct acpi_table_rmrr *)header;
break;
}
}
static int __init
acpi_parse_dmar(unsigned long phys_addr, unsigned long size)
{
struct acpi_table_dmar *dmar = NULL;
struct acpi_dmar_entry_header *entry_header;
int ret = 0;
if (!phys_addr || !size)
return -EINVAL;
dmar = (struct acpi_table_dmar *)__acpi_map_table(phys_addr, size);
if (!dmar) {
printk (KERN_WARNING PREFIX "Unable to map DMAR\n");
return -ENODEV;
}
if (!dmar->haw) {
printk (KERN_WARNING PREFIX "Zero: Invalid DMAR haw\n");
return -EINVAL;
}
dmar_host_address_width = dmar->haw;
printk (KERN_INFO PREFIX "Host address width %d\n",
dmar_host_address_width);
entry_header = (struct acpi_dmar_entry_header *)(dmar + 1);
while (((unsigned long)entry_header) < (((unsigned long)dmar) + size)) {
acpi_table_print_dmar_entry(entry_header);
switch (entry_header->type) {
case ACPI_DMAR_DRHD:
printk (KERN_INFO PREFIX "found ACPI_DMAR_DRHD\n");
ret = acpi_parse_one_drhd(entry_header);
break;
case ACPI_DMAR_RMRR:
printk (KERN_INFO PREFIX "found ACPI_DMAR_RMRR\n");
ret = acpi_parse_one_rmrr(entry_header);
break;
case ACPI_DMAR_ATSR:
printk (KERN_INFO PREFIX "found ACPI_DMAR_RMRR\n");
ret = acpi_parse_one_atsr(entry_header);
break;
default:
printk(KERN_WARNING PREFIX "Unknown DMAR structure type\n");
ret = -EINVAL;
break;
}
if (ret)
break;
entry_header = ((void *)entry_header + entry_header->length);
}
return ret;
}
int acpi_dmar_init(void)
{
acpi_table_parse(ACPI_DMAR, acpi_parse_dmar);
if (list_empty(&acpi_drhd_units)) {
printk(KERN_ERR PREFIX "No DMAR devices found\n");
return -ENODEV;
} else
vtd_enabled = 1;
return 0;
}
xen/arch/x86/hvm/vmx/vtd/dmar.h
+90
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@@ -0,0 +1,90 @@
/*
* Copyright (c) 2006, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
* Place - Suite 330, Boston, MA 02111-1307 USA.
*
* Copyright (C) Ashok Raj <ashok.raj@intel.com>
* Copyright (C) Shaohua Li <shaohua.li@intel.com>
*/
#ifndef _DMAR_H_
#define _DMAR_H_
#include <xen/list.h>
#include <asm/iommu.h>
extern u8 dmar_host_address_width;
struct acpi_drhd_unit {
struct list_head list;
unsigned long address; /* register base address of the unit */
struct pci_dev *devices; /* target devices */
int devices_cnt;
u8 include_all:1;
struct iommu *iommu;
};
struct acpi_rmrr_unit {
struct list_head list;
unsigned long base_address;
unsigned long end_address;
struct pci_dev *devices; /* target devices */
int devices_cnt;
u8 allow_all:1;
};
struct acpi_atsr_unit {
struct list_head list;
struct pci_dev *devices; /* target devices */
int devices_cnt;
u8 all_ports:1;
};
#define for_each_iommu(domain, iommu) \
list_for_each_entry(iommu, \
&(domain->arch.hvm_domain.hvm_iommu.iommu_list), list)
#define for_each_pdev(domain, pdev) \
list_for_each_entry(pdev, \
&(domain->arch.hvm_domain.hvm_iommu.pdev_list), list)
#define for_each_drhd_unit(drhd) \
list_for_each_entry(drhd, &acpi_drhd_units, list)
#define for_each_rmrr_device(rmrr, pdev) \
list_for_each_entry(rmrr, &acpi_rmrr_units, list) { \
int _i; \
for (_i = 0; _i < rmrr->devices_cnt; _i++) { \
pdev = &(rmrr->devices[_i]);
#define end_for_each_rmrr_device(rmrr, pdev) \
} \
}
struct acpi_drhd_unit * acpi_find_matched_drhd_unit(struct pci_dev *dev);
struct acpi_rmrr_unit * acpi_find_matched_rmrr_unit(struct pci_dev *dev);
/* This one is for interrupt remapping */
struct acpi_ioapic_unit {
struct list_head list;
int apic_id;
union {
u16 info;
struct {
u16 bus: 8,
dev: 5,
func: 3;
}bdf;
}ioapic;
};
#endif // _DMAR_H_
xen/arch/x86/hvm/vmx/vtd/intel-iommu.c
+1927
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File diff suppressed because it is too large. Load diff
xen/arch/x86/hvm/vmx/vtd/io.c
+120
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@@ -0,0 +1,120 @@
/*
* Copyright (c) 2006, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
* Place - Suite 330, Boston, MA 02111-1307 USA.
*
* Copyright (C) Allen Kay <allen.m.kay@intel.com>
* Copyright (C) Xiaohui Xin <xiaohui.xin@intel.com>
*/
#include <xen/init.h>
#include <xen/config.h>
#include <xen/init.h>
#include <xen/mm.h>
#include <xen/lib.h>
#include <xen/errno.h>
#include <xen/trace.h>
#include <xen/event.h>
#include <xen/hypercall.h>
#include <asm/current.h>
#include <asm/cpufeature.h>
#include <asm/processor.h>
#include <asm/msr.h>
#include <asm/apic.h>
#include <asm/paging.h>
#include <asm/shadow.h>
#include <asm/p2m.h>
#include <asm/hvm/hvm.h>
#include <asm/hvm/support.h>
#include <asm/hvm/vpt.h>
#include <asm/hvm/vpic.h>
#include <asm/hvm/vlapic.h>
#include <public/sched.h>
#include <xen/iocap.h>
#include <public/hvm/ioreq.h>
int hvm_do_IRQ_dpci(struct domain *d, unsigned int mirq)
{
uint32_t device, intx;
uint32_t link, isa_irq;
struct hvm_irq *hvm_irq;
if (!vtd_enabled || (d == dom0))
return 0;
if (d->arch.hvm_domain.irq.mirq[mirq].valid)
{
device = d->arch.hvm_domain.irq.mirq[mirq].device;
intx = d->arch.hvm_domain.irq.mirq[mirq].intx;
link = hvm_pci_intx_link(device, intx);
hvm_irq = &d->arch.hvm_domain.irq;
isa_irq = hvm_irq->pci_link.route[link];
if ( !d->arch.hvm_domain.irq.girq[isa_irq].valid )
{
d->arch.hvm_domain.irq.girq[isa_irq].valid = 1;
d->arch.hvm_domain.irq.girq[isa_irq].device = device;
d->arch.hvm_domain.irq.girq[isa_irq].intx = intx;
d->arch.hvm_domain.irq.girq[isa_irq].machine_gsi = mirq;
}
if ( !test_and_set_bit(mirq, d->arch.hvm_domain.irq.dirq_mask) )
{
vcpu_kick(d->vcpu[0]);
return 1;
}
else
dprintk(XENLOG_INFO, "Want to pending mirq, but failed\n");
}
return 0;
}
void hvm_dpci_eoi(unsigned int guest_gsi, union vioapic_redir_entry *ent)
{
struct domain *d = current->domain;
uint32_t device, intx, machine_gsi;
irq_desc_t *desc;
if (d->arch.hvm_domain.irq.girq[guest_gsi].valid)
{
device = d->arch.hvm_domain.irq.girq[guest_gsi].device;
intx = d->arch.hvm_domain.irq.girq[guest_gsi].intx;
machine_gsi = d->arch.hvm_domain.irq.girq[guest_gsi].machine_gsi;
gdprintk(XENLOG_INFO, "hvm_dpci_eoi:: device %x intx %x\n",
device, intx);
hvm_pci_intx_deassert(d, device, intx);
if ( (ent == NULL) || (ent && ent->fields.mask == 0) ) {
desc = &irq_desc[irq_to_vector(machine_gsi)];
desc->handler->end(irq_to_vector(machine_gsi));
}
}
}
int release_devices(struct domain *d)
{
struct hvm_domain *hd = &d->arch.hvm_domain;
uint32_t i;
int ret = 0;
if (!vtd_enabled)
return ret;
/* unbind irq */
for (i = 0; i < NR_IRQS; i++) {
if (hd->irq.mirq[i].valid)
ret = pirq_guest_unbind(d, i);
}
iommu_domain_teardown(d);
return ret;
}
xen/arch/x86/hvm/vmx/vtd/msi.h
+128
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@@ -0,0 +1,128 @@
/*
* Copyright (C) 2003-2004 Intel
* Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
*/
#ifndef MSI_H
#define MSI_H
/*
* Assume the maximum number of hot plug slots supported by the system is about
* ten. The worstcase is that each of these slots is hot-added with a device,
* which has two MSI/MSI-X capable functions. To avoid any MSI-X driver, which
* attempts to request all available vectors, NR_HP_RESERVED_VECTORS is defined
* as below to ensure at least one message is assigned to each detected MSI/
* MSI-X device function.
*/
#define NR_HP_RESERVED_VECTORS 20
extern int vector_irq[NR_VECTORS];
extern void (*interrupt[NR_IRQS])(void);
extern int pci_vector_resources(int last, int nr_released);
/*
* MSI-X Address Register
*/
#define PCI_MSIX_FLAGS_QSIZE 0x7FF
#define PCI_MSIX_FLAGS_ENABLE (1 << 15)
#define PCI_MSIX_FLAGS_BIRMASK (7 << 0)
#define PCI_MSIX_FLAGS_BITMASK (1 << 0)
#define PCI_MSIX_ENTRY_SIZE 16
#define PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET 0
#define PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET 4
#define PCI_MSIX_ENTRY_DATA_OFFSET 8
#define PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET 12
#define msi_control_reg(base) (base + PCI_MSI_FLAGS)
#define msi_lower_address_reg(base) (base + PCI_MSI_ADDRESS_LO)
#define msi_upper_address_reg(base) (base + PCI_MSI_ADDRESS_HI)
#define msi_data_reg(base, is64bit) \
( (is64bit == 1) ? base+PCI_MSI_DATA_64 : base+PCI_MSI_DATA_32 )
#define msi_mask_bits_reg(base, is64bit) \
( (is64bit == 1) ? base+PCI_MSI_MASK_BIT : base+PCI_MSI_MASK_BIT-4)
#define msi_disable(control) control &= ~PCI_MSI_FLAGS_ENABLE
#define multi_msi_capable(control) \
(1 << ((control & PCI_MSI_FLAGS_QMASK) >> 1))
#define multi_msi_enable(control, num) \
control |= (((num >> 1) << 4) & PCI_MSI_FLAGS_QSIZE);
#define is_64bit_address(control) (control & PCI_MSI_FLAGS_64BIT)
#define is_mask_bit_support(control) (control & PCI_MSI_FLAGS_MASKBIT)
#define msi_enable(control, num) multi_msi_enable(control, num); \
control |= PCI_MSI_FLAGS_ENABLE
#define msix_table_offset_reg(base) (base + 0x04)
#define msix_pba_offset_reg(base) (base + 0x08)
#define msix_enable(control) control |= PCI_MSIX_FLAGS_ENABLE
#define msix_disable(control) control &= ~PCI_MSIX_FLAGS_ENABLE
#define msix_table_size(control) ((control & PCI_MSIX_FLAGS_QSIZE)+1)
#define multi_msix_capable msix_table_size
#define msix_unmask(address) (address & ~PCI_MSIX_FLAGS_BITMASK)
#define msix_mask(address) (address | PCI_MSIX_FLAGS_BITMASK)
#define msix_is_pending(address) (address & PCI_MSIX_FLAGS_PENDMASK)
/*
* MSI Defined Data Structures
*/
#define MSI_ADDRESS_HEADER 0xfee
#define MSI_ADDRESS_HEADER_SHIFT 12
#define MSI_ADDRESS_HEADER_MASK 0xfff000
#define MSI_ADDRESS_DEST_ID_MASK 0xfff0000f
#define MSI_TARGET_CPU_MASK 0xff
#define MSI_TARGET_CPU_SHIFT 12
#define MSI_DELIVERY_MODE 0
#define MSI_LEVEL_MODE 1 /* Edge always assert */
#define MSI_TRIGGER_MODE 0 /* MSI is edge sensitive */
#define MSI_PHYSICAL_MODE 0
#define MSI_LOGICAL_MODE 1
#define MSI_REDIRECTION_HINT_MODE 0
#define __LITTLE_ENDIAN_BITFIELD 1
struct msg_data {
#if defined(__LITTLE_ENDIAN_BITFIELD)
__u32 vector : 8;
__u32 delivery_mode : 3; /* 000b: FIXED | 001b: lowest prior */
__u32 reserved_1 : 3;
__u32 level : 1; /* 0: deassert | 1: assert */
__u32 trigger : 1; /* 0: edge | 1: level */
__u32 reserved_2 : 16;
#elif defined(__BIG_ENDIAN_BITFIELD)
__u32 reserved_2 : 16;
__u32 trigger : 1; /* 0: edge | 1: level */
__u32 level : 1; /* 0: deassert | 1: assert */
__u32 reserved_1 : 3;
__u32 delivery_mode : 3; /* 000b: FIXED | 001b: lowest prior */
__u32 vector : 8;
#else
#error "Bitfield endianness not defined! Check your byteorder.h"
#endif
} __attribute__ ((packed));
struct msg_address {
union {
struct {
#if defined(__LITTLE_ENDIAN_BITFIELD)
__u32 reserved_1 : 2;
__u32 dest_mode : 1; /*0:physic | 1:logic */
__u32 redirection_hint: 1; /*0: dedicated CPU
1: lowest priority */
__u32 reserved_2 : 4;
__u32 dest_id : 24; /* Destination ID */
#elif defined(__BIG_ENDIAN_BITFIELD)
__u32 dest_id : 24; /* Destination ID */
__u32 reserved_2 : 4;
__u32 redirection_hint: 1; /*0: dedicated CPU
1: lowest priority */
__u32 dest_mode : 1; /*0:physic | 1:logic */
__u32 reserved_1 : 2;
#else
#error "Bitfield endianness not defined! Check your byteorder.h"
#endif
}u;
__u32 value;
}lo_address;
__u32 hi_address;
} __attribute__ ((packed));
#endif /* MSI_H */
xen/arch/x86/hvm/vmx/vtd/pci-direct.h
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#ifndef ASM_PCI_DIRECT_H
#define ASM_PCI_DIRECT_H 1
#include <xen/types.h>
#include <asm/io.h>
/* Direct PCI access. This is used for PCI accesses in early boot before
the PCI subsystem works. */
#define PDprintk(x...)
static inline u32 read_pci_config(u8 bus, u8 slot, u8 func, u8 offset)
{
u32 v;
outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8);
v = inl(0xcfc);
if (v != 0xffffffff)
PDprintk("%x reading 4 from %x: %x\n", slot, offset, v);
return v;
}
static inline u8 read_pci_config_byte(u8 bus, u8 slot, u8 func, u8 offset)
{
u8 v;
outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8);
v = inb(0xcfc + (offset&3));
PDprintk("%x reading 1 from %x: %x\n", slot, offset, v);
return v;
}
static inline u16 read_pci_config_16(u8 bus, u8 slot, u8 func, u8 offset)
{
u16 v;
outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8);
v = inw(0xcfc + (offset&2));
PDprintk("%x reading 2 from %x: %x\n", slot, offset, v);
return v;
}
static inline void write_pci_config(u8 bus, u8 slot, u8 func, u8 offset,
u32 val)
{
PDprintk("%x writing to %x: %x\n", slot, offset, val);
outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8);
outl(val, 0xcfc);
}
#endif
xen/arch/x86/hvm/vmx/vtd/pci_regs.h
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/*
* pci_regs.h
*
* PCI standard defines
* Copyright 1994, Drew Eckhardt
* Copyright 1997--1999 Martin Mares <mj@ucw.cz>
*
* For more information, please consult the following manuals (look at
* http://www.pcisig.com/ for how to get them):
*
* PCI BIOS Specification
* PCI Local Bus Specification
* PCI to PCI Bridge Specification
* PCI System Design Guide
*/
#ifndef LINUX_PCI_REGS_H
#define LINUX_PCI_REGS_H
/*
* Under PCI, each device has 256 bytes of configuration address space,
* of which the first 64 bytes are standardized as follows:
*/
#define PCI_VENDOR_ID 0x00 /* 16 bits */
#define PCI_DEVICE_ID 0x02 /* 16 bits */
#define PCI_COMMAND 0x04 /* 16 bits */
#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
#define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
#define PCI_STATUS 0x06 /* 16 bits */
#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
#define PCI_STATUS_DEVSEL_FAST 0x000
#define PCI_STATUS_DEVSEL_MEDIUM 0x200
#define PCI_STATUS_DEVSEL_SLOW 0x400
#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */
#define PCI_REVISION_ID 0x08 /* Revision ID */
#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
#define PCI_CLASS_DEVICE 0x0a /* Device class */
#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
#define PCI_HEADER_TYPE 0x0e /* 8 bits */
#define PCI_HEADER_TYPE_NORMAL 0
#define PCI_HEADER_TYPE_BRIDGE 1
#define PCI_HEADER_TYPE_CARDBUS 2
#define PCI_BIST 0x0f /* 8 bits */
#define PCI_BIST_CODE_MASK 0x0f /* Return result */
#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
/*
* Base addresses specify locations in memory or I/O space.
* Decoded size can be determined by writing a value of
* 0xffffffff to the register, and reading it back. Only
* 1 bits are decoded.
*/
#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
#define PCI_BASE_ADDRESS_SPACE_IO 0x01
#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
/* bit 1 is reserved if address_space = 1 */
/* Header type 0 (normal devices) */
#define PCI_CARDBUS_CIS 0x28
#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
#define PCI_SUBSYSTEM_ID 0x2e
#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
#define PCI_ROM_ADDRESS_ENABLE 0x01
#define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
/* 0x35-0x3b are reserved */
#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
#define PCI_MIN_GNT 0x3e /* 8 bits */
#define PCI_MAX_LAT 0x3f /* 8 bits */
/* Header type 1 (PCI-to-PCI bridges) */
#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
#define PCI_IO_LIMIT 0x1d
#define PCI_IO_RANGE_TYPE_MASK 0x0fUL /* I/O bridging type */
#define PCI_IO_RANGE_TYPE_16 0x00
#define PCI_IO_RANGE_TYPE_32 0x01
#define PCI_IO_RANGE_MASK (~0x0fUL)
#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
#define PCI_MEMORY_LIMIT 0x22
#define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL
#define PCI_MEMORY_RANGE_MASK (~0x0fUL)
#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
#define PCI_PREF_MEMORY_LIMIT 0x26
#define PCI_PREF_RANGE_TYPE_MASK 0x0fUL
#define PCI_PREF_RANGE_TYPE_32 0x00
#define PCI_PREF_RANGE_TYPE_64 0x01
#define PCI_PREF_RANGE_MASK (~0x0fUL)
#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
#define PCI_PREF_LIMIT_UPPER32 0x2c
#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
#define PCI_IO_LIMIT_UPPER16 0x32
/* 0x34 same as for htype 0 */
/* 0x35-0x3b is reserved */
#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
/* 0x3c-0x3d are same as for htype 0 */
#define PCI_BRIDGE_CONTROL 0x3e
#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
/* Header type 2 (CardBus bridges) */
#define PCI_CB_CAPABILITY_LIST 0x14
/* 0x15 reserved */
#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
#define PCI_CB_MEMORY_BASE_0 0x1c
#define PCI_CB_MEMORY_LIMIT_0 0x20
#define PCI_CB_MEMORY_BASE_1 0x24
#define PCI_CB_MEMORY_LIMIT_1 0x28
#define PCI_CB_IO_BASE_0 0x2c
#define PCI_CB_IO_BASE_0_HI 0x2e
#define PCI_CB_IO_LIMIT_0 0x30
#define PCI_CB_IO_LIMIT_0_HI 0x32
#define PCI_CB_IO_BASE_1 0x34
#define PCI_CB_IO_BASE_1_HI 0x36
#define PCI_CB_IO_LIMIT_1 0x38
#define PCI_CB_IO_LIMIT_1_HI 0x3a
#define PCI_CB_IO_RANGE_MASK (~0x03UL)
/* 0x3c-0x3d are same as for htype 0 */
#define PCI_CB_BRIDGE_CONTROL 0x3e
#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
#define PCI_CB_BRIDGE_CTL_SERR 0x02
#define PCI_CB_BRIDGE_CTL_ISA 0x04
#define PCI_CB_BRIDGE_CTL_VGA 0x08
#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
#define PCI_CB_SUBSYSTEM_ID 0x42
#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
/* 0x48-0x7f reserved */
/* Capability lists */
#define PCI_CAP_LIST_ID 0 /* Capability ID */
#define PCI_CAP_ID_PM 0x01 /* Power Management */
#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
#define PCI_CAP_ID_HT_IRQCONF 0x08 /* HyperTransport IRQ Configuration */
#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
#define PCI_CAP_ID_EXP 0x10 /* PCI Express */
#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
#define PCI_CAP_SIZEOF 4
/* Power Management Registers */
#define PCI_PM_PMC 2 /* PM Capabilities Register */
#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
#define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */
#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
#define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */
#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
#define PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */
#define PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */
#define PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */
#define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */
#define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */
#define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */
#define PCI_PM_CTRL 4 /* PM control and status register */
#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
#define PCI_PM_CTRL_NO_SOFT_RESET 0x0004 /* No reset for D3hot->D0 */
#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
#define PCI_PM_DATA_REGISTER 7 /* (??) */
#define PCI_PM_SIZEOF 8
/* AGP registers */
#define PCI_AGP_VERSION 2 /* BCD version number */
#define PCI_AGP_RFU 3 /* Rest of capability flags */
#define PCI_AGP_STATUS 4 /* Status register */
#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
#define PCI_AGP_COMMAND 8 /* Control register */
#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */
#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */
#define PCI_AGP_SIZEOF 12
/* Vital Product Data */
#define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */
#define PCI_VPD_ADDR_MASK 0x7fff /* Address mask */
#define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */
#define PCI_VPD_DATA 4 /* 32-bits of data returned here */
/* Slot Identification */
#define PCI_SID_ESR 2 /* Expansion Slot Register */
#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
/* Message Signalled Interrupts registers */
#define PCI_MSI_FLAGS 2 /* Various flags */
#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
#define PCI_MSI_FLAGS_MASKBIT 0x100 /* 64-bit mask bits allowed */
#define PCI_MSI_RFU 3 /* Rest of capability flags */
#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
#define PCI_MSI_MASK_BIT 16 /* Mask bits register */
/* CompactPCI Hotswap Register */
#define PCI_CHSWP_CSR 2 /* Control and Status Register */
#define PCI_CHSWP_DHA 0x01 /* Device Hiding Arm */
#define PCI_CHSWP_EIM 0x02 /* ENUM# Signal Mask */
#define PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */
#define PCI_CHSWP_LOO 0x08 /* LED On / Off */
#define PCI_CHSWP_PI 0x30 /* Programming Interface */
#define PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */
#define PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */
/* PCI-X registers */
#define PCI_X_CMD 2 /* Modes & Features */
#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
#define PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */
#define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */
#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */
#define PCI_X_STATUS 4 /* PCI-X capabilities */
#define PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */
#define PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */
#define PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */
#define PCI_X_STATUS_133MHZ 0x00020000 /* 133 MHz capable */
#define PCI_X_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */
#define PCI_X_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */
#define PCI_X_STATUS_COMPLEX 0x00100000 /* Device Complexity */
#define PCI_X_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count */
#define PCI_X_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */
#define PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */
#define PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */
#define PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */
#define PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
/* PCI Express capability registers */
#define PCI_EXP_FLAGS 2 /* Capabilities register */
#define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
#define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
#define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
#define PCI_EXP_DEVCAP 4 /* Device capabilities */
#define PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
#define PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
#define PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
#define PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
#define PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
#define PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
#define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */
#define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
#define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
#define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
#define PCI_EXP_DEVCTL 8 /* Device Control */
#define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */
#define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
#define PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */
#define PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */
#define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
#define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
#define PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
#define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
#define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
#define PCI_EXP_DEVSTA 10 /* Device Status */
#define PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
#define PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
#define PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
#define PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */
#define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
#define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
#define PCI_EXP_LNKCAP 12 /* Link Capabilities */
#define PCI_EXP_LNKCTL 16 /* Link Control */
#define PCI_EXP_LNKSTA 18 /* Link Status */
#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
#define PCI_EXP_SLTCTL 24 /* Slot Control */
#define PCI_EXP_SLTSTA 26 /* Slot Status */
#define PCI_EXP_RTCTL 28 /* Root Control */
#define PCI_EXP_RTCTL_SECEE 0x01 /* System Error on Correctable Error */
#define PCI_EXP_RTCTL_SENFEE 0x02 /* System Error on Non-Fatal Error */
#define PCI_EXP_RTCTL_SEFEE 0x04 /* System Error on Fatal Error */
#define PCI_EXP_RTCTL_PMEIE 0x08 /* PME Interrupt Enable */
#define PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS Software Visibility Enable */
#define PCI_EXP_RTCAP 30 /* Root Capabilities */
#define PCI_EXP_RTSTA 32 /* Root Status */
/* Extended Capabilities (PCI-X 2.0 and Express) */
#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
#define PCI_EXT_CAP_ID_ERR 1
#define PCI_EXT_CAP_ID_VC 2
#define PCI_EXT_CAP_ID_DSN 3
#define PCI_EXT_CAP_ID_PWR 4
/* Advanced Error Reporting */
#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */
#define PCI_ERR_UNC_TRAIN 0x00000001 /* Training */
#define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */
#define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */
#define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */
#define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */
#define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort */
#define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */
#define PCI_ERR_UNC_RX_OVER 0x00020000 /* Receiver Overflow */
#define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */
#define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */
#define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */
#define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */
/* Same bits as above */
#define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */
/* Same bits as above */
#define PCI_ERR_COR_STATUS 16 /* Correctable Error Status */
#define PCI_ERR_COR_RCVR 0x00000001 /* Receiver Error Status */
#define PCI_ERR_COR_BAD_TLP 0x00000040 /* Bad TLP Status */
#define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */
#define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */
#define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */
#define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */
/* Same bits as above */
#define PCI_ERR_CAP 24 /* Advanced Error Capabilities */
#define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */
#define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */
#define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */
#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */
#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */
#define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */
#define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */
#define PCI_ERR_ROOT_STATUS 48
#define PCI_ERR_ROOT_COR_SRC 52
#define PCI_ERR_ROOT_SRC 54
/* Virtual Channel */
#define PCI_VC_PORT_REG1 4
#define PCI_VC_PORT_REG2 8
#define PCI_VC_PORT_CTRL 12
#define PCI_VC_PORT_STATUS 14
#define PCI_VC_RES_CAP 16
#define PCI_VC_RES_CTRL 20
#define PCI_VC_RES_STATUS 26
/* Power Budgeting */
#define PCI_PWR_DSR 4 /* Data Select Register */
#define PCI_PWR_DATA 8 /* Data Register */
#define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */
#define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */
#define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */
#define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */
#define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */
#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */
#define PCI_PWR_CAP 12 /* Capability */
#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */
#endif /* LINUX_PCI_REGS_H */
xen/arch/x86/hvm/vmx/vtd/utils.c
+302
View File
@@ -0,0 +1,302 @@
/*
* Copyright (c) 2006, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
* Place - Suite 330, Boston, MA 02111-1307 USA.
*
* Copyright (C) Allen Kay <allen.m.kay@intel.com>
*/
#include <xen/init.h>
#include <xen/bitmap.h>
#include <xen/irq.h>
#include <xen/spinlock.h>
#include <xen/sched.h>
#include <asm/delay.h>
#include <asm/iommu.h>
#include <asm/hvm/vmx/intel-iommu.h>
#include "dmar.h"
#include "pci-direct.h"
#include "pci_regs.h"
#include "msi.h"
#include <xen/mm.h>
#include <xen/xmalloc.h>
#if defined(__x86_64__)
void print_iommu_regs(struct acpi_drhd_unit *drhd)
{
struct iommu *iommu = drhd->iommu;
printk("---- print_iommu_regs ----\n");
printk("print_iommu_regs: drhd->address = %lx\n", drhd->address);
printk("print_iommu_regs: DMAR_VER_REG = %x\n",
dmar_readl(iommu->reg,DMAR_VER_REG));
printk("print_iommu_regs: DMAR_CAP_REG = %lx\n",
dmar_readq(iommu->reg,DMAR_CAP_REG));
printk("print_iommu_regs: n_fault_reg = %lx\n",
cap_num_fault_regs(dmar_readq(iommu->reg, DMAR_CAP_REG)));
printk("print_iommu_regs: fault_recording_offset_l = %lx\n",
cap_fault_reg_offset(dmar_readq(iommu->reg, DMAR_CAP_REG)));
printk("print_iommu_regs: fault_recording_offset_h = %lx\n",
cap_fault_reg_offset(dmar_readq(iommu->reg, DMAR_CAP_REG)) + 8);
printk("print_iommu_regs: fault_recording_reg_l = %lx\n",
dmar_readq(iommu->reg, cap_fault_reg_offset(dmar_readq(iommu->reg, DMAR_CAP_REG))));
printk("print_iommu_regs: fault_recording_reg_h = %lx\n",
dmar_readq(iommu->reg, cap_fault_reg_offset(dmar_readq(iommu->reg, DMAR_CAP_REG)) + 8));
printk("print_iommu_regs: DMAR_ECAP_REG = %lx\n",
dmar_readq(iommu->reg,DMAR_ECAP_REG));
printk("print_iommu_regs: DMAR_GCMD_REG = %x\n",
dmar_readl(iommu->reg,DMAR_GCMD_REG));
printk("print_iommu_regs: DMAR_GSTS_REG = %x\n",
dmar_readl(iommu->reg,DMAR_GSTS_REG));
printk("print_iommu_regs: DMAR_RTADDR_REG = %lx\n",
dmar_readq(iommu->reg,DMAR_RTADDR_REG));
printk("print_iommu_regs: DMAR_CCMD_REG = %lx\n",
dmar_readq(iommu->reg,DMAR_CCMD_REG));
printk("print_iommu_regs: DMAR_FSTS_REG = %x\n",
dmar_readl(iommu->reg,DMAR_FSTS_REG));
printk("print_iommu_regs: DMAR_FECTL_REG = %x\n",
dmar_readl(iommu->reg,DMAR_FECTL_REG));
printk("print_iommu_regs: DMAR_FEDATA_REG = %x\n",
dmar_readl(iommu->reg,DMAR_FEDATA_REG));
printk("print_iommu_regs: DMAR_FEADDR_REG = %x\n",
dmar_readl(iommu->reg,DMAR_FEADDR_REG));
printk("print_iommu_regs: DMAR_FEUADDR_REG = %x\n",
dmar_readl(iommu->reg,DMAR_FEUADDR_REG));
}
void print_vtd_entries(struct domain *d, int bus, int devfn,
unsigned long gmfn)
{
struct hvm_iommu *hd = domain_hvm_iommu(d);
struct acpi_drhd_unit *drhd;
struct iommu *iommu;
struct context_entry *ctxt_entry;
struct root_entry *root_entry;
u64 *l3, *l2, *l1;
u32 l3_index, l2_index, l1_index;
u32 i = 0;
printk("print_vtd_entries: domain_id = %x bdf = %x:%x:%x devfn = %x, gmfn = %lx\n", d->domain_id, bus, PCI_SLOT(devfn), PCI_FUNC(devfn), devfn, gmfn);
for_each_drhd_unit(drhd) {
printk("---- print_vtd_entries %d ----\n", i++);
if (hd->pgd == NULL) {
printk(" hg->pgd == NULL\n");
return;
}
iommu = drhd->iommu;
root_entry = iommu->root_entry;
printk(" hd->pgd = %p virt_to_maddr(hd->pgd) = %lx\n",
hd->pgd, virt_to_maddr(hd->pgd));
printk(" root_entry = %p\n", root_entry);
if (root_entry == NULL) {
printk(" root_entry == NULL\n");
return;
}
printk(" root_entry[%x] = %lx\n", bus, root_entry[bus].val);
printk(" maddr_to_virt(root_entry[%x]) = %p\n",
bus, maddr_to_virt(root_entry[bus].val));
if (root_entry[bus].val == 0) {
printk(" root_entry[%x].lo == 0\n", bus);
return;
}
ctxt_entry = maddr_to_virt((root_entry[bus].val >> PAGE_SHIFT) << PAGE_SHIFT);
if (ctxt_entry == NULL) {
printk(" ctxt_entry == NULL\n");
return;
}
if (ctxt_entry[devfn].lo == 0) {
printk(" ctxt_entry[%x].lo == 0\n", devfn);
return;
}
printk(" context = %p\n", ctxt_entry);
printk(" context[%x] = %lx %lx\n",
devfn, ctxt_entry[devfn].hi, ctxt_entry[devfn].lo);
printk(" maddr_to_virt(context[%x].lo) = %p\n",
devfn, maddr_to_virt(ctxt_entry[devfn].lo));
printk(" context[%x] = %lx\n", devfn, ctxt_entry[devfn].lo);
l3 = maddr_to_virt(ctxt_entry[devfn].lo);
l3 = (u64*)(((u64) l3 >> PAGE_SHIFT_4K) << PAGE_SHIFT_4K);
printk(" l3 = %p\n", l3);
if (l3 == NULL) return;
l3_index = (gmfn >> 9 >> 9) & 0x1ff;
printk(" l3_index = %x\n", l3_index);
printk(" l3[%x] = %lx\n", l3_index, l3[l3_index]);
l2 = maddr_to_virt(l3[l3_index]);
l2 = (u64*)(((u64) l2 >> PAGE_SHIFT_4K) << PAGE_SHIFT_4K);
printk(" l2 = %p\n", l2);
if (l2 == NULL) return;
l2_index = (gmfn >> 9) & 0x1ff;
printk(" gmfn = %lx\n", gmfn);
printk(" gmfn >> 9= %lx\n", gmfn >> 9);
printk(" l2_index = %x\n", l2_index);
printk(" l2[%x] = %lx\n", l2_index, l2[l2_index]);
l1 = maddr_to_virt(l2[l2_index]);
l1 = (u64*)(((u64) l1 >> PAGE_SHIFT_4K) << PAGE_SHIFT_4K);
if (l1 == NULL) return;
l1_index = gmfn & 0x1ff;
printk(" l1 = %p\n", l1);
printk(" l1_index = %x\n", l1_index);
printk(" l1[%x] = %lx\n", l1_index, l1[l1_index]);
}
}
#else // !m64
void print_iommu_regs(struct acpi_drhd_unit *drhd)
{
struct iommu *iommu = drhd->iommu;
printk("---- print_iommu_regs ----\n");
printk("print_iommu_regs: drhd->address = %lx\n", drhd->address);
printk("print_iommu_regs: DMAR_VER_REG = %x\n",
dmar_readl(iommu->reg,DMAR_VER_REG));
printk("print_iommu_regs: DMAR_CAP_REG = %llx\n",
dmar_readq(iommu->reg,DMAR_CAP_REG));
printk("print_iommu_regs: n_fault_reg = %llx\n",
cap_num_fault_regs(dmar_readq(iommu->reg, DMAR_CAP_REG)));
printk("print_iommu_regs: fault_recording_offset_l = %llx\n",
cap_fault_reg_offset(dmar_readq(iommu->reg, DMAR_CAP_REG)));
printk("print_iommu_regs: fault_recording_offset_h = %llx\n",
cap_fault_reg_offset(dmar_readq(iommu->reg, DMAR_CAP_REG)) + 8);
printk("print_iommu_regs: fault_recording_reg_l = %llx\n",
dmar_readq(iommu->reg, cap_fault_reg_offset(dmar_readq(iommu->reg, DMAR_CAP_REG))));
printk("print_iommu_regs: fault_recording_reg_h = %llx\n",
dmar_readq(iommu->reg, cap_fault_reg_offset(dmar_readq(iommu->reg, DMAR_CAP_REG)) + 8));
printk("print_iommu_regs: DMAR_ECAP_REG = %llx\n",
dmar_readq(iommu->reg,DMAR_ECAP_REG));
printk("print_iommu_regs: DMAR_GCMD_REG = %x\n",
dmar_readl(iommu->reg,DMAR_GCMD_REG));
printk("print_iommu_regs: DMAR_GSTS_REG = %x\n",
dmar_readl(iommu->reg,DMAR_GSTS_REG));
printk("print_iommu_regs: DMAR_RTADDR_REG = %llx\n",
dmar_readq(iommu->reg,DMAR_RTADDR_REG));
printk("print_iommu_regs: DMAR_CCMD_REG = %llx\n",
dmar_readq(iommu->reg,DMAR_CCMD_REG));
printk("print_iommu_regs: DMAR_FSTS_REG = %x\n",
dmar_readl(iommu->reg,DMAR_FSTS_REG));
printk("print_iommu_regs: DMAR_FECTL_REG = %x\n",
dmar_readl(iommu->reg,DMAR_FECTL_REG));
printk("print_iommu_regs: DMAR_FEDATA_REG = %x\n",
dmar_readl(iommu->reg,DMAR_FEDATA_REG));
printk("print_iommu_regs: DMAR_FEADDR_REG = %x\n",
dmar_readl(iommu->reg,DMAR_FEADDR_REG));
printk("print_iommu_regs: DMAR_FEUADDR_REG = %x\n",
dmar_readl(iommu->reg,DMAR_FEUADDR_REG));
}
void print_vtd_entries(struct domain *d, int bus, int devfn,
unsigned long gmfn)
{
struct hvm_iommu *hd = domain_hvm_iommu(d);
struct acpi_drhd_unit *drhd;
struct iommu *iommu;
struct context_entry *ctxt_entry;
struct root_entry *root_entry;
u64 *l3, *l2, *l1;
u32 l3_index, l2_index, l1_index;
u32 i = 0;
printk("print_vtd_entries: domain_id = %x bdf = %x:%x:%x devfn = %x, gmfn = %lx\n", d->domain_id, bus, PCI_SLOT(devfn), PCI_FUNC(devfn), devfn, gmfn);
for_each_drhd_unit(drhd) {
printk("---- print_vtd_entries %d ----\n", i++);
if (hd->pgd == NULL) {
printk(" hg->pgd == NULL\n");
return;
}
iommu = drhd->iommu;
root_entry = iommu->root_entry;
printk(" d->pgd = %p virt_to_maddr(hd->pgd) = %lx\n",
hd->pgd, virt_to_maddr(hd->pgd));
printk(" root_entry = %p\n", root_entry);
if (root_entry == NULL) {
printk(" root_entry == NULL\n");
return;
}
printk(" root_entry[%x] = %llx\n", bus, root_entry[bus].val);
printk(" maddr_to_virt(root_entry[%x]) = %p\n",
bus, maddr_to_virt(root_entry[bus].val));
if (root_entry[bus].val == 0) {
printk(" root_entry[%x].lo == 0\n", bus);
return;
}
ctxt_entry = maddr_to_virt((root_entry[bus].val >> PAGE_SHIFT) << PAGE_SHIFT);
if (ctxt_entry == NULL) {
printk(" ctxt_entry == NULL\n");
return;
}
if (ctxt_entry[devfn].lo == 0) {
printk(" ctxt_entry[%x].lo == 0\n", devfn);
return;
}
printk(" context = %p\n", ctxt_entry);
printk(" context[%x] = %llx %llx\n",
devfn, ctxt_entry[devfn].hi, ctxt_entry[devfn].lo);
printk(" maddr_to_virt(context[%x].lo) = %p\n",
devfn, maddr_to_virt(ctxt_entry[devfn].lo));
printk(" context[%x] = %llx\n", devfn, ctxt_entry[devfn].lo);
l3 = maddr_to_virt(ctxt_entry[devfn].lo);
l3 = (u64*)(((u32) l3 >> PAGE_SHIFT_4K) << PAGE_SHIFT_4K);
printk(" l3 = %p\n", l3);
if (l3 == NULL) return;
l3_index = (gmfn >> 9 >> 9) & 0x1ff;
printk(" l3_index = %x\n", l3_index);
printk(" l3[%x] = %llx\n", l3_index, l3[l3_index]);
l2 = maddr_to_virt(l3[l3_index]);
l2 = (u64*)(((u32) l2 >> PAGE_SHIFT_4K) << PAGE_SHIFT_4K);
printk(" l2 = %p\n", l2);
if (l2 == NULL) return;
l2_index = (gmfn >> 9) & 0x1ff;
printk(" gmfn = %lx\n", gmfn);
printk(" gmfn >> 9= %lx\n", gmfn >> 9);
printk(" l2_index = %x\n", l2_index);
printk(" l2[%x] = %llx\n", l2_index, l2[l2_index]);
l1 = maddr_to_virt(l2[l2_index]);
l1 = (u64*)(((u32) l1 >> PAGE_SHIFT_4K) << PAGE_SHIFT_4K);
if (l1 == NULL) return;
l1_index = gmfn & 0x1ff;
printk(" l1 = %p\n", l1);
printk(" l1_index = %x\n", l1_index);
printk(" l1[%x] = %llx\n", l1_index, l1[l1_index]);
}
}
#endif // !m64
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