x86/msr: Virtualise MSR_SPEC_CTRL.SSBD for guests to use

Almost all infrastructure is already in place.  Update the reserved bits
calculation in guest_wrmsr(), and offer SSBD to guests by default.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
This commit is contained in:
Andrew Cooper committed 2018-05-21 14:20:06 +01:00
1 parent 9df52a25e0
commit cd53023df9
2 files changed
+7 -3

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+6 -2
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@@ -197,6 +197,8 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val)
switch ( msr )
{
uint64_t rsvd;
case MSR_INTEL_PLATFORM_INFO:
case MSR_ARCH_CAPABILITIES:
/* Read-only */
@@ -232,8 +234,10 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val)
* Note: SPEC_CTRL_STIBP is specified as safe to use (i.e. ignored)
* when STIBP isn't enumerated in hardware.
*/
rsvd = ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP |
(cp->feat.ssbd ? SPEC_CTRL_SSBD : 0));
if ( val & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP) )
if ( val & rsvd )
goto gp_fault; /* Rsvd bit set? */
vp->spec_ctrl.raw = val;
@@ -252,12 +256,12 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val)
case MSR_INTEL_MISC_FEATURES_ENABLES:
{
uint64_t rsvd = ~0ull;
bool old_cpuid_faulting = vp->misc_features_enables.cpuid_faulting;
if ( !vp->misc_features_enables.available )
goto gp_fault;
rsvd = ~0ull;
if ( dp->plaform_info.cpuid_faulting )
rsvd &= ~MSR_MISC_FEATURES_CPUID_FAULTING;
+1 -1
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@@ -245,7 +245,7 @@ XEN_CPUFEATURE(AVX512_4FMAPS, 9*32+ 3) /*A AVX512 Multiply Accumulation Single
XEN_CPUFEATURE(IBRSB, 9*32+26) /*A IBRS and IBPB support (used by Intel) */
XEN_CPUFEATURE(STIBP, 9*32+27) /*A! STIBP */
XEN_CPUFEATURE(ARCH_CAPS, 9*32+29) /* IA32_ARCH_CAPABILITIES MSR */
XEN_CPUFEATURE(SSBD, 9*32+31) /* MSR_SPEC_CTRL.SSBD available */
XEN_CPUFEATURE(SSBD, 9*32+31) /*A MSR_SPEC_CTRL.SSBD available */
#endif /* XEN_CPUFEATURE */
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