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x86/spec-ctrl: Enumeration for new Intel BHI controls
https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/branch-history-injection.html Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Reviewed-by: Jan Beulich <jbeulich@suse.com>
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@@ -36,7 +36,12 @@
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#define SPEC_CTRL_IBRS (_AC(1, ULL) << 0)
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#define SPEC_CTRL_STIBP (_AC(1, ULL) << 1)
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#define SPEC_CTRL_SSBD (_AC(1, ULL) << 2)
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#define SPEC_CTRL_IPRED_DIS_U (_AC(1, ULL) << 3)
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#define SPEC_CTRL_IPRED_DIS_S (_AC(1, ULL) << 4)
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#define SPEC_CTRL_RRSBA_DIS_U (_AC(1, ULL) << 5)
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#define SPEC_CTRL_RRSBA_DIS_S (_AC(1, ULL) << 6)
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#define SPEC_CTRL_PSFD (_AC(1, ULL) << 7)
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#define SPEC_CTRL_BHI_DIS_S (_AC(1, ULL) << 10)
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#define MSR_PRED_CMD 0x00000049
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#define PRED_CMD_IBPB (_AC(1, ULL) << 0)
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@@ -66,6 +71,8 @@
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#define ARCH_CAPS_IF_PSCHANGE_MC_NO (_AC(1, ULL) << 6)
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#define ARCH_CAPS_TSX_CTRL (_AC(1, ULL) << 7)
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#define ARCH_CAPS_TAA_NO (_AC(1, ULL) << 8)
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#define ARCH_CAPS_RRSBA (_AC(1, ULL) << 19)
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#define ARCH_CAPS_BHI_NO (_AC(1, ULL) << 20)
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#define MSR_FLUSH_CMD 0x0000010b
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#define FLUSH_CMD_L1D (_AC(1, ULL) << 0)
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@@ -304,6 +304,9 @@ XEN_CPUFEATURE(INTEL_PPIN, 12*32+ 0) /* Protected Processor Inventory
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/* Intel-defined CPU features, CPUID level 0x00000007:2.edx, word 13 */
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XEN_CPUFEATURE(INTEL_PSFD, 13*32+ 0) /*A MSR_SPEC_CTRL.PSFD */
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XEN_CPUFEATURE(IPRED_CTRL, 13*32+ 1) /* MSR_SPEC_CTRL.IPRED_DIS_* */
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XEN_CPUFEATURE(RRSBA_CTRL, 13*32+ 2) /* MSR_SPEC_CTRL.RRSBA_DIS_* */
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XEN_CPUFEATURE(BHI_CTRL, 13*32+ 4) /* MSR_SPEC_CTRL.BHI_DIS_S */
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XEN_CPUFEATURE(MCDT_NO, 13*32+ 5) /*A MCDT_NO */
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#endif /* XEN_CPUFEATURE */
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