From d1f70074a59d3ee267c9462d3bef45e44be5bff6 Mon Sep 17 00:00:00 2001 From: Jiaqing Zhao Date: Thu, 2 Jul 2026 08:46:12 +0200 Subject: [PATCH] ns16550: add support for ASIX AX99100 PCIe Multi-I/O controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a PCI device table entry and matching parameter for the ASIX AX99100 PCIe to Multi-I/O controller [125b:9910]. Each port on the chip is a standalone PCI function, with UART registers on its I/O BAR0. Signed-off-by: Jiaqing Zhao Reviewed-by: Stefano Stabellini Acked-by: Roger Pau Monné --- xen/drivers/char/ns16550.c | 15 +++++++++++++++ xen/include/xen/pci_ids.h | 2 ++ 2 files changed, 17 insertions(+) diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c index 916bb7325e..120ac09d23 100644 --- a/xen/drivers/char/ns16550.c +++ b/xen/drivers/char/ns16550.c @@ -97,6 +97,7 @@ struct ns16550_config { param_exar_xr17v358, param_intel_lpss, param_wch_ch382, + param_asix, } param; }; @@ -900,6 +901,14 @@ static const struct ns16550_config_param __initconst uart_param[] = { .bar0 = true, .max_ports = 2, }, + [param_asix] = { + .base_baud = 115200, + .reg_width = 1, + .fifo_size = 256, + .lsr_mask = UART_LSR_THRE, + .bar0 = true, + .max_ports = 1, + }, }; static const struct ns16550_config __initconst uart_config[] = @@ -1240,6 +1249,12 @@ static const struct ns16550_config __initconst uart_config[] = .dev_id = 0x3253, .param = param_wch_ch382 }, + /* ASIX AX99100 PCIe to Multi I/O Controller */ + { + .vendor_id = PCI_VENDOR_ID_ASIX, + .dev_id = 0x9910, + .param = param_asix + }, }; static int __init diff --git a/xen/include/xen/pci_ids.h b/xen/include/xen/pci_ids.h index 15e938225c..fd424ef55d 100644 --- a/xen/include/xen/pci_ids.h +++ b/xen/include/xen/pci_ids.h @@ -5,6 +5,8 @@ #define PCI_VENDOR_ID_NVIDIA 0x10de +#define PCI_VENDOR_ID_ASIX 0x125b + #define PCI_VENDOR_ID_PERICOM 0x12d8 #define PCI_VENDOR_ID_EXAR 0x13a8