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x86: rename XMM* features to SSE*
The latter are their canonical names, used already in the instruction emulator. Signed-off-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
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Jan Beulich committed
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5 files changed
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@@ -205,12 +205,12 @@ static void __init early_cpu_detect(void)
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c->x86_model += ((eax >> 16) & 0xF) << 4;
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c->x86_mask = eax & 15;
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edx &= ~cleared_caps[cpufeat_word(X86_FEATURE_FPU)];
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ecx &= ~cleared_caps[cpufeat_word(X86_FEATURE_XMM3)];
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ecx &= ~cleared_caps[cpufeat_word(X86_FEATURE_SSE3)];
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if (edx & cpufeat_mask(X86_FEATURE_CLFLUSH))
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c->x86_cache_alignment = ((ebx >> 8) & 0xff) * 8;
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/* Leaf 0x1 capabilities filled in early for Xen. */
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c->x86_capability[cpufeat_word(X86_FEATURE_FPU)] = edx;
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c->x86_capability[cpufeat_word(X86_FEATURE_XMM3)] = ecx;
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c->x86_capability[cpufeat_word(X86_FEATURE_SSE3)] = ecx;
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if ( cpuid_eax(0x80000000) >= 0x80000008 )
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paddr_bits = cpuid_eax(0x80000008) & 0xff;
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@@ -249,7 +249,7 @@ static void generic_identify(struct cpuinfo_x86 *c)
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c->cpuid_level = cpuid_eax(0);
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cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
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c->x86_capability[cpufeat_word(X86_FEATURE_FPU)] = edx;
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c->x86_capability[cpufeat_word(X86_FEATURE_XMM3)] = ecx;
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c->x86_capability[cpufeat_word(X86_FEATURE_SSE3)] = ecx;
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if ( cpu_has(c, X86_FEATURE_CLFLUSH) )
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c->x86_clflush_size = ((ebx >> 8) & 0xff) * 8;
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@@ -2029,7 +2029,7 @@ unsigned long hvm_cr4_guest_reserved_bits(const struct vcpu *v,bool_t restore)
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X86_CR4_PCE |
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(leaf1_edx & cpufeat_mask(X86_FEATURE_FXSR) ?
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X86_CR4_OSFXSR : 0) |
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(leaf1_edx & cpufeat_mask(X86_FEATURE_XMM) ?
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(leaf1_edx & cpufeat_mask(X86_FEATURE_SSE) ?
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X86_CR4_OSXMMEXCPT : 0) |
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((restore || nestedhvm_enabled(v->domain)) &&
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(leaf1_ecx & cpufeat_mask(X86_FEATURE_VMXE)) ?
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@@ -1963,7 +1963,7 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content)
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data |= X86_CR4_PGE;
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if ( edx & cpufeat_mask(X86_FEATURE_FXSR) )
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data |= X86_CR4_OSFXSR;
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if ( edx & cpufeat_mask(X86_FEATURE_XMM) )
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if ( edx & cpufeat_mask(X86_FEATURE_SSE) )
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data |= X86_CR4_OSXMMEXCPT;
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if ( ecx & cpufeat_mask(X86_FEATURE_VMXE) )
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data |= X86_CR4_VMXE;
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@@ -22,7 +22,7 @@
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cpufeat_mask(X86_FEATURE_CMOV) | cpufeat_mask(X86_FEATURE_PAT) | \
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cpufeat_mask(X86_FEATURE_PSE36) | cpufeat_mask(X86_FEATURE_CLFLUSH)| \
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cpufeat_mask(X86_FEATURE_MMX) | cpufeat_mask(X86_FEATURE_FXSR) | \
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cpufeat_mask(X86_FEATURE_XMM) | cpufeat_mask(X86_FEATURE_XMM2))
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cpufeat_mask(X86_FEATURE_SSE) | cpufeat_mask(X86_FEATURE_SSE2))
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#define AMD_EXTFEATURES_K8_REV_C_ECX 0
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#define AMD_EXTFEATURES_K8_REV_C_EDX ( \
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cpufeat_mask(X86_FEATURE_FPU) | cpufeat_mask(X86_FEATURE_VME) | \
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@@ -48,7 +48,7 @@
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/* Family 0Fh, Revision E */
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#define AMD_FEATURES_K8_REV_E_ECX (AMD_FEATURES_K8_REV_D_ECX | \
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cpufeat_mask(X86_FEATURE_XMM3))
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cpufeat_mask(X86_FEATURE_SSE3))
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#define AMD_FEATURES_K8_REV_E_EDX (AMD_FEATURES_K8_REV_D_EDX | \
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cpufeat_mask(X86_FEATURE_HT))
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#define AMD_EXTFEATURES_K8_REV_E_ECX (AMD_EXTFEATURES_K8_REV_D_ECX |\
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@@ -38,8 +38,8 @@
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#define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */
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#define X86_FEATURE_FXSR (0*32+24) /* FXSAVE and FXRSTOR instructions (fast save and restore */
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/* of FPU context), and CR4.OSFXSR available */
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#define X86_FEATURE_XMM (0*32+25) /* Streaming SIMD Extensions */
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#define X86_FEATURE_XMM2 (0*32+26) /* Streaming SIMD Extensions-2 */
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#define X86_FEATURE_SSE (0*32+25) /* Streaming SIMD Extensions */
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#define X86_FEATURE_SSE2 (0*32+26) /* Streaming SIMD Extensions-2 */
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#define X86_FEATURE_SELFSNOOP (0*32+27) /* CPU self snoop */
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#define X86_FEATURE_HT (0*32+28) /* Hyper-Threading */
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#define X86_FEATURE_ACC (0*32+29) /* Automatic clock control */
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@@ -78,7 +78,7 @@
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#define X86_FEATURE_APERFMPERF (3*32+16) /* APERFMPERF */
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/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
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#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */
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#define X86_FEATURE_SSE3 (4*32+ 0) /* Streaming SIMD Extensions-3 */
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#define X86_FEATURE_PCLMULQDQ (4*32+ 1) /* Carry-less mulitplication */
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#define X86_FEATURE_DTES64 (4*32+ 2) /* 64-bit Debug Store */
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#define X86_FEATURE_MWAIT (4*32+ 3) /* Monitor/Mwait support */
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@@ -183,7 +183,9 @@
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#define cpu_has_sep boot_cpu_has(X86_FEATURE_SEP)
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#define cpu_has_mtrr 1
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#define cpu_has_mmx 1
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#define cpu_has_xmm3 boot_cpu_has(X86_FEATURE_XMM3)
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#define cpu_has_sse boot_cpu_has(X86_FEATURE_SSE)
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#define cpu_has_sse2 boot_cpu_has(X86_FEATURE_SSE2)
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#define cpu_has_sse3 boot_cpu_has(X86_FEATURE_SSE3)
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#define cpu_has_ht boot_cpu_has(X86_FEATURE_HT)
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#define cpu_has_mp 1
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#define cpu_has_nx boot_cpu_has(X86_FEATURE_NX)
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