diff --git a/tools/libxl/libxl_cpuid.c b/tools/libxl/libxl_cpuid.c index 8292654c86..3c00bb5c1d 100644 --- a/tools/libxl/libxl_cpuid.c +++ b/tools/libxl/libxl_cpuid.c @@ -160,6 +160,7 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str) {"fpu", 0x00000001, NA, CPUID_REG_EDX, 0, 1}, {"ibrsb", 0x00000007, 0, CPUID_REG_EDX, 26, 1}, {"stibp", 0x00000007, 0, CPUID_REG_EDX, 27, 1}, + {"arch-caps", 0x00000007, 0, CPUID_REG_EDX, 29, 1}, {"topoext", 0x80000001, NA, CPUID_REG_ECX, 22, 1}, {"tbm", 0x80000001, NA, CPUID_REG_ECX, 21, 1}, {"nodeid", 0x80000001, NA, CPUID_REG_ECX, 19, 1}, diff --git a/tools/misc/xen-cpuid.c b/tools/misc/xen-cpuid.c index 0981366e06..06a9c7fffc 100644 --- a/tools/misc/xen-cpuid.c +++ b/tools/misc/xen-cpuid.c @@ -152,8 +152,9 @@ static const char *str_7d0[32] = [0 ... 25] = "REZ", [26] = "ibrsb", [27] = "stibp", + [28] = "REZ", [29] = "arch_caps", - [28 ... 31] = "REZ", + [30 ... 31] = "REZ", }; static struct { diff --git a/xen/arch/x86/mm.c b/xen/arch/x86/mm.c index 78ba28b4c6..eb4b221f89 100644 --- a/xen/arch/x86/mm.c +++ b/xen/arch/x86/mm.c @@ -4015,7 +4015,7 @@ long do_mmu_update( * to the page lock we hold, its pinned status, and uses on * this (v)CPU. */ - if ( !rc && this_cpu(root_pgt) && + if ( !rc && !cpu_has_no_xpti && ((page->u.inuse.type_info & PGT_count_mask) > (1 + !!(page->u.inuse.type_info & PGT_pinned) + (pagetable_get_pfn(curr->arch.guest_table) == mfn) + diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c index 54e2395e9d..cbdc041d09 100644 --- a/xen/arch/x86/setup.c +++ b/xen/arch/x86/setup.c @@ -157,6 +157,9 @@ static void __init parse_smap_param(char *s) } custom_param("smap", parse_smap_param); +static int8_t __initdata opt_xpti = -1; +boolean_param("xpti", opt_xpti); + bool_t __read_mostly acpi_disabled; bool_t __initdata acpi_force; static char __initdata acpi_param[10] = ""; @@ -1480,6 +1483,22 @@ void __init noreturn __start_xen(unsigned long mbi_p) cr4_pv32_mask = mmu_cr4_features & XEN_CR4_PV32_BITS; + if ( opt_xpti < 0 ) + { + uint64_t caps = 0; + + if ( boot_cpu_data.x86_vendor == X86_VENDOR_AMD ) + caps = ARCH_CAPABILITIES_RDCL_NO; + else if ( boot_cpu_has(X86_FEATURE_ARCH_CAPS) ) + rdmsrl(MSR_ARCH_CAPABILITIES, caps); + + opt_xpti = !(caps & ARCH_CAPABILITIES_RDCL_NO); + } + if ( opt_xpti ) + setup_clear_cpu_cap(X86_FEATURE_NO_XPTI); + else + setup_force_cpu_cap(X86_FEATURE_NO_XPTI); + if ( cpu_has_fsgsbase ) set_in_cr4(X86_CR4_FSGSBASE); diff --git a/xen/arch/x86/smpboot.c b/xen/arch/x86/smpboot.c index 58949d5fc9..2b404a0e43 100644 --- a/xen/arch/x86/smpboot.c +++ b/xen/arch/x86/smpboot.c @@ -748,8 +748,6 @@ static int clone_mapping(const void *ptr, root_pgentry_t *rpt) return 0; } -static __read_mostly int8_t opt_xpti = -1; -boolean_param("xpti", opt_xpti); DEFINE_PER_CPU(root_pgentry_t *, root_pgt); static root_pgentry_t common_pgt; @@ -762,7 +760,7 @@ static int setup_cpu_root_pgt(unsigned int cpu) unsigned int off; int rc; - if ( !opt_xpti ) + if ( cpu_has_no_xpti ) return 0; rpt = alloc_xen_pagetable(); @@ -1035,9 +1033,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus) stack_base[0] = stack_start; - if ( opt_xpti < 0 ) - opt_xpti = boot_cpu_data.x86_vendor != X86_VENDOR_AMD; - rc = setup_cpu_root_pgt(0); if ( rc ) panic("Error %d setting up PV root page table\n", rc); diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h index 1074f4b0c9..16cc730e4b 100644 --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -29,6 +29,7 @@ XEN_CPUFEATURE(XEN_IBRS_SET, (FSCAPINTS+0)*32+18) /* IBRSB && IRBS set in Xen XEN_CPUFEATURE(XEN_IBRS_CLEAR, (FSCAPINTS+0)*32+19) /* IBRSB && IBRS clear in Xen */ XEN_CPUFEATURE(RSB_NATIVE, (FSCAPINTS+0)*32+20) /* RSB overwrite needed for native */ XEN_CPUFEATURE(RSB_VMEXIT, (FSCAPINTS+0)*32+21) /* RSB overwrite needed for vmexit */ +XEN_CPUFEATURE(NO_XPTI, (FSCAPINTS+0)*32+22) /* XPTI mitigation not in use */ #define NCAPINTS (FSCAPINTS + 1) /* N 32-bit words worth of info */ @@ -105,6 +106,7 @@ XEN_CPUFEATURE(RSB_VMEXIT, (FSCAPINTS+0)*32+21) /* RSB overwrite needed for #define cpu_has_hypervisor boot_cpu_has(X86_FEATURE_HYPERVISOR) #define cpu_has_cmp_legacy boot_cpu_has(X86_FEATURE_CMP_LEGACY) #define cpu_has_lfence_dispatch boot_cpu_has(X86_FEATURE_LFENCE_DISPATCH) +#define cpu_has_no_xpti boot_cpu_has(X86_FEATURE_NO_XPTI) enum _cache_type { CACHE_TYPE_NULL = 0, diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h index 05ad0b979c..dfc02ae2fd 100644 --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -40,6 +40,8 @@ #define PRED_CMD_IBPB (_AC(1, ULL) << 0) #define MSR_ARCH_CAPABILITIES 0x0000010a +#define ARCH_CAPABILITIES_RDCL_NO (_AC(1, ULL) << 0) +#define ARCH_CAPABILITIES_IBRS_ALL (_AC(1, ULL) << 1) /* Intel MSRs. Some also available on other CPUs */ #define MSR_IA32_PERFCTR0 0x000000c1 diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h index 7457cb8a4c..ef358cf343 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -238,6 +238,7 @@ XEN_CPUFEATURE(IBPB, 8*32+12) /*A IBPB support only (no IBRS, used by /* Intel-defined CPU features, CPUID level 0x00000007:0.edx, word 9 */ XEN_CPUFEATURE(IBRSB, 9*32+26) /*A IBRS and IBPB support (used by Intel) */ XEN_CPUFEATURE(STIBP, 9*32+27) /*A! STIBP */ +XEN_CPUFEATURE(ARCH_CAPS, 9*32+29) /* IA32_ARCH_CAPABILITIES MSR */ #endif /* XEN_CPUFEATURE */