mirror of
https://github.com/xen-project/xen.git
synced 2026-10-28 02:01:24 +01:00
tools: drop ia64 support
Removed support from libxc and mini-os. This also took me under xen/include/public via various symlinks. Dropped tools/debugger/xenitp entirely, it was described upon commit as: "Xenitp is a low-level debugger for ia64" and doesn't appear to be linked into the build anywhere. 99 files changed, 14 insertions(+), 32361 deletions(-) Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Keir Fraser <keir@xen.org> Committed-by: Ian Campbell <ian.campbell@citrix.com>
This commit is contained in:
Ian Campbell committed
1 parent
2fcb3c6fc7
commit
e567964a54
103 files changed
+31
-32399
No files matched your search
@@ -1,32 +0,0 @@
|
||||
XEN_ROOT=$(CURDIR)/../../..
|
||||
include $(XEN_ROOT)/tools/Rules.mk
|
||||
|
||||
#CFLAGS += -Werror -g -O0
|
||||
|
||||
CFLAGS += $(CFLAGS_libxenctrl)
|
||||
|
||||
LIBBIN =
|
||||
|
||||
ifeq ($(XEN_TARGET_ARCH),ia64)
|
||||
LIBBIN += xenitp
|
||||
endif
|
||||
|
||||
.PHONY: all
|
||||
all: build
|
||||
|
||||
.PHONY: build
|
||||
build: $(LIBBIN)
|
||||
|
||||
.PHONY: install
|
||||
install: build
|
||||
[ -z "$(LIBBIN)" ] || $(INSTALL_DIR) $(DESTDIR)$(PRIVATE_BINDIR)
|
||||
[ -z "$(LIBBIN)" ] || $(INSTALL_PROG) $(LIBBIN) $(DESTDIR)$(PRIVATE_BINDIR)
|
||||
|
||||
.PHONY: clean
|
||||
clean:
|
||||
$(RM) *.a *.so *.o *.rpm $(LIBBIN)
|
||||
|
||||
XENITP_OBJS=xenitp.o ia64-dis.o ia64-opc.o cpu-ia64-opc.o
|
||||
|
||||
xenitp: $(XENITP_OBJS)
|
||||
$(CC) $(CFLAGS) -o $@ $(XENITP_OBJS) $(LDLIBS_libxenctrl)
|
||||
@@ -1,36 +0,0 @@
|
||||
xenitp README
|
||||
*************
|
||||
|
||||
|
||||
Xenitp is a low-level, non-symbolic debugger. It only works on ia64.
|
||||
|
||||
* Building xenitp
|
||||
First do 'make tools' at the top level to build libxc and includes. Then
|
||||
cd to tools/debugger/xenitp and do make.
|
||||
|
||||
* Using xenitp
|
||||
Usage is: xenitp DOM
|
||||
DOM is a domain number.
|
||||
'help' shows all the command available.
|
||||
When the domain is running, C-c stops it.
|
||||
|
||||
* Source origin
|
||||
All these files come from binutils:
|
||||
cpu-ia64-opc.c
|
||||
dis-asm.h
|
||||
ia64-asmtab.c
|
||||
ia64-asmtab.h
|
||||
ia64-dis.c
|
||||
ia64-gen.c
|
||||
ia64.h
|
||||
ia64-opc-a.c
|
||||
ia64-opc-b.c
|
||||
ia64-opc.c
|
||||
ia64-opc-d.c
|
||||
ia64-opc-f.c
|
||||
ia64-opc.h
|
||||
ia64-opc-i.c
|
||||
ia64-opc-m.c
|
||||
ia64-opc-x.c
|
||||
|
||||
xenitp.c is based on xenctxt.c
|
||||
@@ -1,615 +0,0 @@
|
||||
/* Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2006
|
||||
Free Software Foundation, Inc.
|
||||
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
|
||||
|
||||
This file is part of BFD, the Binary File Descriptor library.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
|
||||
|
||||
/* Logically, this code should be part of libopcode but since some of
|
||||
the operand insertion/extraction functions help bfd to implement
|
||||
relocations, this code is included as part of cpu-ia64.c. This
|
||||
avoids circular dependencies between libopcode and libbfd and also
|
||||
obviates the need for applications to link in libopcode when all
|
||||
they really want is libbfd.
|
||||
|
||||
--davidm Mon Apr 13 22:14:02 1998 */
|
||||
|
||||
#include "ia64-opc.h"
|
||||
|
||||
#define NELEMS(a) ((int) (sizeof (a) / sizeof ((a)[0])))
|
||||
|
||||
static const char*
|
||||
ins_rsvd (const struct ia64_operand *self ATTRIBUTE_UNUSED,
|
||||
ia64_insn value ATTRIBUTE_UNUSED, ia64_insn *code ATTRIBUTE_UNUSED)
|
||||
{
|
||||
return "internal error---this shouldn't happen";
|
||||
}
|
||||
|
||||
static const char*
|
||||
ext_rsvd (const struct ia64_operand *self ATTRIBUTE_UNUSED,
|
||||
ia64_insn code ATTRIBUTE_UNUSED, ia64_insn *valuep ATTRIBUTE_UNUSED)
|
||||
{
|
||||
return "internal error---this shouldn't happen";
|
||||
}
|
||||
|
||||
static const char*
|
||||
ins_const (const struct ia64_operand *self ATTRIBUTE_UNUSED,
|
||||
ia64_insn value ATTRIBUTE_UNUSED, ia64_insn *code ATTRIBUTE_UNUSED)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const char*
|
||||
ext_const (const struct ia64_operand *self ATTRIBUTE_UNUSED,
|
||||
ia64_insn code ATTRIBUTE_UNUSED, ia64_insn *valuep ATTRIBUTE_UNUSED)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const char*
|
||||
ins_reg (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
|
||||
{
|
||||
if (value >= 1u << self->field[0].bits)
|
||||
return "register number out of range";
|
||||
|
||||
*code |= value << self->field[0].shift;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const char*
|
||||
ext_reg (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
|
||||
{
|
||||
*valuep = ((code >> self->field[0].shift)
|
||||
& ((1u << self->field[0].bits) - 1));
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const char*
|
||||
ins_immu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
|
||||
{
|
||||
ia64_insn new = 0;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
|
||||
{
|
||||
new |= ((value & ((((ia64_insn) 1) << self->field[i].bits) - 1))
|
||||
<< self->field[i].shift);
|
||||
value >>= self->field[i].bits;
|
||||
}
|
||||
if (value)
|
||||
return "integer operand out of range";
|
||||
|
||||
*code |= new;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const char*
|
||||
ext_immu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
|
||||
{
|
||||
BFD_HOST_U_64_BIT value = 0;
|
||||
int i, bits = 0, total = 0;
|
||||
|
||||
for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
|
||||
{
|
||||
bits = self->field[i].bits;
|
||||
value |= ((code >> self->field[i].shift)
|
||||
& ((((BFD_HOST_U_64_BIT) 1) << bits) - 1)) << total;
|
||||
total += bits;
|
||||
}
|
||||
*valuep = value;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const char*
|
||||
ins_immu5b (const struct ia64_operand *self, ia64_insn value,
|
||||
ia64_insn *code)
|
||||
{
|
||||
if (value < 32 || value > 63)
|
||||
return "value must be between 32 and 63";
|
||||
return ins_immu (self, value - 32, code);
|
||||
}
|
||||
|
||||
static const char*
|
||||
ext_immu5b (const struct ia64_operand *self, ia64_insn code,
|
||||
ia64_insn *valuep)
|
||||
{
|
||||
const char *result;
|
||||
|
||||
result = ext_immu (self, code, valuep);
|
||||
if (result)
|
||||
return result;
|
||||
|
||||
*valuep = *valuep + 32;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const char*
|
||||
ins_immus8 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
|
||||
{
|
||||
if (value & 0x7)
|
||||
return "value not an integer multiple of 8";
|
||||
return ins_immu (self, value >> 3, code);
|
||||
}
|
||||
|
||||
static const char*
|
||||
ext_immus8 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
|
||||
{
|
||||
const char *result;
|
||||
|
||||
result = ext_immu (self, code, valuep);
|
||||
if (result)
|
||||
return result;
|
||||
|
||||
*valuep = *valuep << 3;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const char*
|
||||
ins_imms_scaled (const struct ia64_operand *self, ia64_insn value,
|
||||
ia64_insn *code, int scale)
|
||||
{
|
||||
BFD_HOST_64_BIT svalue = value, sign_bit = 0;
|
||||
ia64_insn new = 0;
|
||||
int i;
|
||||
|
||||
svalue >>= scale;
|
||||
|
||||
for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
|
||||
{
|
||||
new |= ((svalue & ((((ia64_insn) 1) << self->field[i].bits) - 1))
|
||||
<< self->field[i].shift);
|
||||
sign_bit = (svalue >> (self->field[i].bits - 1)) & 1;
|
||||
svalue >>= self->field[i].bits;
|
||||
}
|
||||
if ((!sign_bit && svalue != 0) || (sign_bit && svalue != -1))
|
||||
return "integer operand out of range";
|
||||
|
||||
*code |= new;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const char*
|
||||
ext_imms_scaled (const struct ia64_operand *self, ia64_insn code,
|
||||
ia64_insn *valuep, int scale)
|
||||
{
|
||||
int i, bits = 0, total = 0;
|
||||
BFD_HOST_64_BIT val = 0, sign;
|
||||
|
||||
for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
|
||||
{
|
||||
bits = self->field[i].bits;
|
||||
val |= ((code >> self->field[i].shift)
|
||||
& ((((BFD_HOST_U_64_BIT) 1) << bits) - 1)) << total;
|
||||
total += bits;
|
||||
}
|
||||
/* sign extend: */
|
||||
sign = (BFD_HOST_64_BIT) 1 << (total - 1);
|
||||
val = (val ^ sign) - sign;
|
||||
|
||||
*valuep = (val << scale);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const char*
|
||||
ins_imms (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
|
||||
{
|
||||
return ins_imms_scaled (self, value, code, 0);
|
||||
}
|
||||
|
||||
static const char*
|
||||
ins_immsu4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
|
||||
{
|
||||
value = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
|
||||
|
||||
return ins_imms_scaled (self, value, code, 0);
|
||||
}
|
||||
|
||||
static const char*
|
||||
ext_imms (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
|
||||
{
|
||||
return ext_imms_scaled (self, code, valuep, 0);
|
||||
}
|
||||
|
||||
static const char*
|
||||
ins_immsm1 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
|
||||
{
|
||||
--value;
|
||||
return ins_imms_scaled (self, value, code, 0);
|
||||
}
|
||||
|
||||
static const char*
|
||||
ins_immsm1u4 (const struct ia64_operand *self, ia64_insn value,
|
||||
ia64_insn *code)
|
||||
{
|
||||
value = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
|
||||
|
||||
--value;
|
||||
return ins_imms_scaled (self, value, code, 0);
|
||||
}
|
||||
|
||||
static const char*
|
||||
ext_immsm1 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
|
||||
{
|
||||
const char *res = ext_imms_scaled (self, code, valuep, 0);
|
||||
|
||||
++*valuep;
|
||||
return res;
|
||||
}
|
||||
|
||||
static const char*
|
||||
ins_imms1 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
|
||||
{
|
||||
return ins_imms_scaled (self, value, code, 1);
|
||||
}
|
||||
|
||||
static const char*
|
||||
ext_imms1 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
|
||||
{
|
||||
return ext_imms_scaled (self, code, valuep, 1);
|
||||
}
|
||||
|
||||
static const char*
|
||||
ins_imms4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
|
||||
{
|
||||
return ins_imms_scaled (self, value, code, 4);
|
||||
}
|
||||
|
||||
static const char*
|
||||
ext_imms4 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
|
||||
{
|
||||
return ext_imms_scaled (self, code, valuep, 4);
|
||||
}
|
||||
|
||||
static const char*
|
||||
ins_imms16 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
|
||||
{
|
||||
return ins_imms_scaled (self, value, code, 16);
|
||||
}
|
||||
|
||||
static const char*
|
||||
ext_imms16 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
|
||||
{
|
||||
return ext_imms_scaled (self, code, valuep, 16);
|
||||
}
|
||||
|
||||
static const char*
|
||||
ins_cimmu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
|
||||
{
|
||||
ia64_insn mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
|
||||
return ins_immu (self, value ^ mask, code);
|
||||
}
|
||||
|
||||
static const char*
|
||||
ext_cimmu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
|
||||
{
|
||||
const char *result;
|
||||
ia64_insn mask;
|
||||
|
||||
mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
|
||||
result = ext_immu (self, code, valuep);
|
||||
if (!result)
|
||||
{
|
||||
mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
|
||||
*valuep ^= mask;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
static const char*
|
||||
ins_cnt (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
|
||||
{
|
||||
--value;
|
||||
if (value >= ((BFD_HOST_U_64_BIT) 1) << self->field[0].bits)
|
||||
return "count out of range";
|
||||
|
||||
*code |= value << self->field[0].shift;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const char*
|
||||
ext_cnt (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
|
||||
{
|
||||
*valuep = ((code >> self->field[0].shift)
|
||||
& ((((BFD_HOST_U_64_BIT) 1) << self->field[0].bits) - 1)) + 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const char*
|
||||
ins_cnt2b (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
|
||||
{
|
||||
--value;
|
||||
|
||||
if (value > 2)
|
||||
return "count must be in range 1..3";
|
||||
|
||||
*code |= value << self->field[0].shift;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const char*
|
||||
ext_cnt2b (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
|
||||
{
|
||||
*valuep = ((code >> self->field[0].shift) & 0x3) + 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const char*
|
||||
ins_cnt2c (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
|
||||
{
|
||||
switch (value)
|
||||
{
|
||||
case 0: value = 0; break;
|
||||
case 7: value = 1; break;
|
||||
case 15: value = 2; break;
|
||||
case 16: value = 3; break;
|
||||
default: return "count must be 0, 7, 15, or 16";
|
||||
}
|
||||
*code |= value << self->field[0].shift;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const char*
|
||||
ext_cnt2c (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
|
||||
{
|
||||
ia64_insn value;
|
||||
|
||||
value = (code >> self->field[0].shift) & 0x3;
|
||||
switch (value)
|
||||
{
|
||||
case 0: value = 0; break;
|
||||
case 1: value = 7; break;
|
||||
case 2: value = 15; break;
|
||||
case 3: value = 16; break;
|
||||
}
|
||||
*valuep = value;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const char*
|
||||
ins_inc3 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
|
||||
{
|
||||
BFD_HOST_64_BIT val = value;
|
||||
BFD_HOST_U_64_BIT sign = 0;
|
||||
|
||||
if (val < 0)
|
||||
{
|
||||
sign = 0x4;
|
||||
value = -value;
|
||||
}
|
||||
switch (value)
|
||||
{
|
||||
case 1: value = 3; break;
|
||||
case 4: value = 2; break;
|
||||
case 8: value = 1; break;
|
||||
case 16: value = 0; break;
|
||||
default: return "count must be +/- 1, 4, 8, or 16";
|
||||
}
|
||||
*code |= (sign | value) << self->field[0].shift;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const char*
|
||||
ext_inc3 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
|
||||
{
|
||||
BFD_HOST_64_BIT val;
|
||||
int negate;
|
||||
|
||||
val = (code >> self->field[0].shift) & 0x7;
|
||||
negate = val & 0x4;
|
||||
switch (val & 0x3)
|
||||
{
|
||||
case 0: val = 16; break;
|
||||
case 1: val = 8; break;
|
||||
case 2: val = 4; break;
|
||||
case 3: val = 1; break;
|
||||
}
|
||||
if (negate)
|
||||
val = -val;
|
||||
|
||||
*valuep = val;
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define CST IA64_OPND_CLASS_CST
|
||||
#define REG IA64_OPND_CLASS_REG
|
||||
#define IND IA64_OPND_CLASS_IND
|
||||
#define ABS IA64_OPND_CLASS_ABS
|
||||
#define REL IA64_OPND_CLASS_REL
|
||||
|
||||
#define SDEC IA64_OPND_FLAG_DECIMAL_SIGNED
|
||||
#define UDEC IA64_OPND_FLAG_DECIMAL_UNSIGNED
|
||||
|
||||
const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] =
|
||||
{
|
||||
/* constants: */
|
||||
{ CST, ins_const, ext_const, "NIL", {{ 0, 0}}, 0, "<none>" },
|
||||
{ CST, ins_const, ext_const, "ar.csd", {{ 0, 0}}, 0, "ar.csd" },
|
||||
{ CST, ins_const, ext_const, "ar.ccv", {{ 0, 0}}, 0, "ar.ccv" },
|
||||
{ CST, ins_const, ext_const, "ar.pfs", {{ 0, 0}}, 0, "ar.pfs" },
|
||||
{ CST, ins_const, ext_const, "1", {{ 0, 0}}, 0, "1" },
|
||||
{ CST, ins_const, ext_const, "8", {{ 0, 0}}, 0, "8" },
|
||||
{ CST, ins_const, ext_const, "16", {{ 0, 0}}, 0, "16" },
|
||||
{ CST, ins_const, ext_const, "r0", {{ 0, 0}}, 0, "r0" },
|
||||
{ CST, ins_const, ext_const, "ip", {{ 0, 0}}, 0, "ip" },
|
||||
{ CST, ins_const, ext_const, "pr", {{ 0, 0}}, 0, "pr" },
|
||||
{ CST, ins_const, ext_const, "pr.rot", {{ 0, 0}}, 0, "pr.rot" },
|
||||
{ CST, ins_const, ext_const, "psr", {{ 0, 0}}, 0, "psr" },
|
||||
{ CST, ins_const, ext_const, "psr.l", {{ 0, 0}}, 0, "psr.l" },
|
||||
{ CST, ins_const, ext_const, "psr.um", {{ 0, 0}}, 0, "psr.um" },
|
||||
|
||||
/* register operands: */
|
||||
{ REG, ins_reg, ext_reg, "ar", {{ 7, 20}}, 0, /* AR3 */
|
||||
"an application register" },
|
||||
{ REG, ins_reg, ext_reg, "b", {{ 3, 6}}, 0, /* B1 */
|
||||
"a branch register" },
|
||||
{ REG, ins_reg, ext_reg, "b", {{ 3, 13}}, 0, /* B2 */
|
||||
"a branch register"},
|
||||
{ REG, ins_reg, ext_reg, "cr", {{ 7, 20}}, 0, /* CR */
|
||||
"a control register"},
|
||||
{ REG, ins_reg, ext_reg, "f", {{ 7, 6}}, 0, /* F1 */
|
||||
"a floating-point register" },
|
||||
{ REG, ins_reg, ext_reg, "f", {{ 7, 13}}, 0, /* F2 */
|
||||
"a floating-point register" },
|
||||
{ REG, ins_reg, ext_reg, "f", {{ 7, 20}}, 0, /* F3 */
|
||||
"a floating-point register" },
|
||||
{ REG, ins_reg, ext_reg, "f", {{ 7, 27}}, 0, /* F4 */
|
||||
"a floating-point register" },
|
||||
{ REG, ins_reg, ext_reg, "p", {{ 6, 6}}, 0, /* P1 */
|
||||
"a predicate register" },
|
||||
{ REG, ins_reg, ext_reg, "p", {{ 6, 27}}, 0, /* P2 */
|
||||
"a predicate register" },
|
||||
{ REG, ins_reg, ext_reg, "r", {{ 7, 6}}, 0, /* R1 */
|
||||
"a general register" },
|
||||
{ REG, ins_reg, ext_reg, "r", {{ 7, 13}}, 0, /* R2 */
|
||||
"a general register" },
|
||||
{ REG, ins_reg, ext_reg, "r", {{ 7, 20}}, 0, /* R3 */
|
||||
"a general register" },
|
||||
{ REG, ins_reg, ext_reg, "r", {{ 2, 20}}, 0, /* R3_2 */
|
||||
"a general register r0-r3" },
|
||||
|
||||
/* memory operands: */
|
||||
{ IND, ins_reg, ext_reg, "", {{7, 20}}, 0, /* MR3 */
|
||||
"a memory address" },
|
||||
|
||||
/* indirect operands: */
|
||||
{ IND, ins_reg, ext_reg, "cpuid", {{7, 20}}, 0, /* CPUID_R3 */
|
||||
"a cpuid register" },
|
||||
{ IND, ins_reg, ext_reg, "dbr", {{7, 20}}, 0, /* DBR_R3 */
|
||||
"a dbr register" },
|
||||
{ IND, ins_reg, ext_reg, "dtr", {{7, 20}}, 0, /* DTR_R3 */
|
||||
"a dtr register" },
|
||||
{ IND, ins_reg, ext_reg, "itr", {{7, 20}}, 0, /* ITR_R3 */
|
||||
"an itr register" },
|
||||
{ IND, ins_reg, ext_reg, "ibr", {{7, 20}}, 0, /* IBR_R3 */
|
||||
"an ibr register" },
|
||||
{ IND, ins_reg, ext_reg, "msr", {{7, 20}}, 0, /* MSR_R3 */
|
||||
"an msr register" },
|
||||
{ IND, ins_reg, ext_reg, "pkr", {{7, 20}}, 0, /* PKR_R3 */
|
||||
"a pkr register" },
|
||||
{ IND, ins_reg, ext_reg, "pmc", {{7, 20}}, 0, /* PMC_R3 */
|
||||
"a pmc register" },
|
||||
{ IND, ins_reg, ext_reg, "pmd", {{7, 20}}, 0, /* PMD_R3 */
|
||||
"a pmd register" },
|
||||
{ IND, ins_reg, ext_reg, "rr", {{7, 20}}, 0, /* RR_R3 */
|
||||
"an rr register" },
|
||||
|
||||
/* immediate operands: */
|
||||
{ ABS, ins_cimmu, ext_cimmu, 0, {{ 5, 20 }}, UDEC, /* CCNT5 */
|
||||
"a 5-bit count (0-31)" },
|
||||
{ ABS, ins_cnt, ext_cnt, 0, {{ 2, 27 }}, UDEC, /* CNT2a */
|
||||
"a 2-bit count (1-4)" },
|
||||
{ ABS, ins_cnt2b, ext_cnt2b, 0, {{ 2, 27 }}, UDEC, /* CNT2b */
|
||||
"a 2-bit count (1-3)" },
|
||||
{ ABS, ins_cnt2c, ext_cnt2c, 0, {{ 2, 30 }}, UDEC, /* CNT2c */
|
||||
"a count (0, 7, 15, or 16)" },
|
||||
{ ABS, ins_immu, ext_immu, 0, {{ 5, 14}}, UDEC, /* CNT5 */
|
||||
"a 5-bit count (0-31)" },
|
||||
{ ABS, ins_immu, ext_immu, 0, {{ 6, 27}}, UDEC, /* CNT6 */
|
||||
"a 6-bit count (0-63)" },
|
||||
{ ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 20}}, UDEC, /* CPOS6a */
|
||||
"a 6-bit bit pos (0-63)" },
|
||||
{ ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 14}}, UDEC, /* CPOS6b */
|
||||
"a 6-bit bit pos (0-63)" },
|
||||
{ ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 31}}, UDEC, /* CPOS6c */
|
||||
"a 6-bit bit pos (0-63)" },
|
||||
{ ABS, ins_imms, ext_imms, 0, {{ 1, 36}}, SDEC, /* IMM1 */
|
||||
"a 1-bit integer (-1, 0)" },
|
||||
{ ABS, ins_immu, ext_immu, 0, {{ 2, 13}}, UDEC, /* IMMU2 */
|
||||
"a 2-bit unsigned (0-3)" },
|
||||
{ ABS, ins_immu5b, ext_immu5b, 0, {{ 5, 14}}, UDEC, /* IMMU5b */
|
||||
"a 5-bit unsigned (32 + (0-31))" },
|
||||
{ ABS, ins_immu, ext_immu, 0, {{ 7, 13}}, 0, /* IMMU7a */
|
||||
"a 7-bit unsigned (0-127)" },
|
||||
{ ABS, ins_immu, ext_immu, 0, {{ 7, 20}}, 0, /* IMMU7b */
|
||||
"a 7-bit unsigned (0-127)" },
|
||||
{ ABS, ins_immu, ext_immu, 0, {{ 7, 13}}, UDEC, /* SOF */
|
||||
"a frame size (register count)" },
|
||||
{ ABS, ins_immu, ext_immu, 0, {{ 7, 20}}, UDEC, /* SOL */
|
||||
"a local register count" },
|
||||
{ ABS, ins_immus8,ext_immus8,0, {{ 4, 27}}, UDEC, /* SOR */
|
||||
"a rotating register count (integer multiple of 8)" },
|
||||
{ ABS, ins_imms, ext_imms, 0, /* IMM8 */
|
||||
{{ 7, 13}, { 1, 36}}, SDEC,
|
||||
"an 8-bit integer (-128-127)" },
|
||||
{ ABS, ins_immsu4, ext_imms, 0, /* IMM8U4 */
|
||||
{{ 7, 13}, { 1, 36}}, SDEC,
|
||||
"an 8-bit signed integer for 32-bit unsigned compare (-128-127)" },
|
||||
{ ABS, ins_immsm1, ext_immsm1, 0, /* IMM8M1 */
|
||||
{{ 7, 13}, { 1, 36}}, SDEC,
|
||||
"an 8-bit integer (-127-128)" },
|
||||
{ ABS, ins_immsm1u4, ext_immsm1, 0, /* IMM8M1U4 */
|
||||
{{ 7, 13}, { 1, 36}}, SDEC,
|
||||
"an 8-bit integer for 32-bit unsigned compare (-127-(-1),1-128,0x100000000)" },
|
||||
{ ABS, ins_immsm1, ext_immsm1, 0, /* IMM8M1U8 */
|
||||
{{ 7, 13}, { 1, 36}}, SDEC,
|
||||
"an 8-bit integer for 64-bit unsigned compare (-127-(-1),1-128,0x10000000000000000)" },
|
||||
{ ABS, ins_immu, ext_immu, 0, {{ 2, 33}, { 7, 20}}, 0, /* IMMU9 */
|
||||
"a 9-bit unsigned (0-511)" },
|
||||
{ ABS, ins_imms, ext_imms, 0, /* IMM9a */
|
||||
{{ 7, 6}, { 1, 27}, { 1, 36}}, SDEC,
|
||||
"a 9-bit integer (-256-255)" },
|
||||
{ ABS, ins_imms, ext_imms, 0, /* IMM9b */
|
||||
{{ 7, 13}, { 1, 27}, { 1, 36}}, SDEC,
|
||||
"a 9-bit integer (-256-255)" },
|
||||
{ ABS, ins_imms, ext_imms, 0, /* IMM14 */
|
||||
{{ 7, 13}, { 6, 27}, { 1, 36}}, SDEC,
|
||||
"a 14-bit integer (-8192-8191)" },
|
||||
{ ABS, ins_imms1, ext_imms1, 0, /* IMM17 */
|
||||
{{ 7, 6}, { 8, 24}, { 1, 36}}, 0,
|
||||
"a 17-bit integer (-65536-65535)" },
|
||||
{ ABS, ins_immu, ext_immu, 0, {{20, 6}, { 1, 36}}, 0, /* IMMU21 */
|
||||
"a 21-bit unsigned" },
|
||||
{ ABS, ins_imms, ext_imms, 0, /* IMM22 */
|
||||
{{ 7, 13}, { 9, 27}, { 5, 22}, { 1, 36}}, SDEC,
|
||||
"a 22-bit signed integer" },
|
||||
{ ABS, ins_immu, ext_immu, 0, /* IMMU24 */
|
||||
{{21, 6}, { 2, 31}, { 1, 36}}, 0,
|
||||
"a 24-bit unsigned" },
|
||||
{ ABS, ins_imms16,ext_imms16,0, {{27, 6}, { 1, 36}}, 0, /* IMM44 */
|
||||
"a 44-bit unsigned (least 16 bits ignored/zeroes)" },
|
||||
{ ABS, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* IMMU62 */
|
||||
"a 62-bit unsigned" },
|
||||
{ ABS, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* IMMU64 */
|
||||
"a 64-bit unsigned" },
|
||||
{ ABS, ins_inc3, ext_inc3, 0, {{ 3, 13}}, SDEC, /* INC3 */
|
||||
"an increment (+/- 1, 4, 8, or 16)" },
|
||||
{ ABS, ins_cnt, ext_cnt, 0, {{ 4, 27}}, UDEC, /* LEN4 */
|
||||
"a 4-bit length (1-16)" },
|
||||
{ ABS, ins_cnt, ext_cnt, 0, {{ 6, 27}}, UDEC, /* LEN6 */
|
||||
"a 6-bit length (1-64)" },
|
||||
{ ABS, ins_immu, ext_immu, 0, {{ 4, 20}}, 0, /* MBTYPE4 */
|
||||
"a mix type (@rev, @mix, @shuf, @alt, or @brcst)" },
|
||||
{ ABS, ins_immu, ext_immu, 0, {{ 8, 20}}, 0, /* MBTYPE8 */
|
||||
"an 8-bit mix type" },
|
||||
{ ABS, ins_immu, ext_immu, 0, {{ 6, 14}}, UDEC, /* POS6 */
|
||||
"a 6-bit bit pos (0-63)" },
|
||||
{ REL, ins_imms4, ext_imms4, 0, {{ 7, 6}, { 2, 33}}, 0, /* TAG13 */
|
||||
"a branch tag" },
|
||||
{ REL, ins_imms4, ext_imms4, 0, {{ 9, 24}}, 0, /* TAG13b */
|
||||
"a branch tag" },
|
||||
{ REL, ins_imms4, ext_imms4, 0, {{20, 6}, { 1, 36}}, 0, /* TGT25 */
|
||||
"a branch target" },
|
||||
{ REL, ins_imms4, ext_imms4, 0, /* TGT25b */
|
||||
{{ 7, 6}, {13, 20}, { 1, 36}}, 0,
|
||||
"a branch target" },
|
||||
{ REL, ins_imms4, ext_imms4, 0, {{20, 13}, { 1, 36}}, 0, /* TGT25c */
|
||||
"a branch target" },
|
||||
{ REL, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* TGT64 */
|
||||
"a branch target" },
|
||||
|
||||
{ ABS, ins_const, ext_const, 0, {{0, 0}}, 0, /* LDXMOV */
|
||||
"ldxmov target" },
|
||||
};
|
||||
@@ -1,548 +0,0 @@
|
||||
/* Interface between the opcode library and its callers.
|
||||
|
||||
Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005
|
||||
Free Software Foundation, Inc.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
||||
any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 51 Franklin Street - Fifth Floor,
|
||||
Boston, MA 02110-1301, USA.
|
||||
|
||||
Written by Cygnus Support, 1993.
|
||||
|
||||
The opcode library (libopcodes.a) provides instruction decoders for
|
||||
a large variety of instruction sets, callable with an identical
|
||||
interface, for making instruction-processing programs more independent
|
||||
of the instruction set being processed. */
|
||||
|
||||
#ifndef DIS_ASM_H
|
||||
#define DIS_ASM_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <inttypes.h>
|
||||
|
||||
#define PARAMS(x) x
|
||||
typedef void *PTR;
|
||||
typedef uint64_t bfd_vma;
|
||||
typedef int64_t bfd_signed_vma;
|
||||
typedef uint8_t bfd_byte;
|
||||
typedef int bfd_boolean;
|
||||
#define BFD_HOST_U_64_BIT unsigned long
|
||||
#define BFD_HOST_64_BIT long
|
||||
#define sprintf_vma(s,x) sprintf (s, "%0" PRIx64, x)
|
||||
|
||||
extern unsigned long bfd_getl64 (const bfd_byte *addr);
|
||||
|
||||
#define BFD64
|
||||
#define ATTRIBUTE_FPTR_PRINTF_2
|
||||
#define ATTRIBUTE_UNUSED __attribute__((unused))
|
||||
|
||||
enum bfd_flavour {
|
||||
bfd_target_unknown_flavour,
|
||||
bfd_target_aout_flavour,
|
||||
bfd_target_coff_flavour,
|
||||
bfd_target_ecoff_flavour,
|
||||
bfd_target_elf_flavour,
|
||||
bfd_target_ieee_flavour,
|
||||
bfd_target_nlm_flavour,
|
||||
bfd_target_oasys_flavour,
|
||||
bfd_target_tekhex_flavour,
|
||||
bfd_target_srec_flavour,
|
||||
bfd_target_ihex_flavour,
|
||||
bfd_target_som_flavour,
|
||||
bfd_target_os9k_flavour,
|
||||
bfd_target_versados_flavour,
|
||||
bfd_target_msdos_flavour,
|
||||
bfd_target_evax_flavour
|
||||
};
|
||||
|
||||
enum bfd_endian { BFD_ENDIAN_BIG, BFD_ENDIAN_LITTLE, BFD_ENDIAN_UNKNOWN };
|
||||
|
||||
enum bfd_architecture
|
||||
{
|
||||
bfd_arch_unknown, /* File arch not known */
|
||||
bfd_arch_obscure, /* Arch known, not one of these */
|
||||
bfd_arch_m68k, /* Motorola 68xxx */
|
||||
#define bfd_mach_m68000 1
|
||||
#define bfd_mach_m68008 2
|
||||
#define bfd_mach_m68010 3
|
||||
#define bfd_mach_m68020 4
|
||||
#define bfd_mach_m68030 5
|
||||
#define bfd_mach_m68040 6
|
||||
#define bfd_mach_m68060 7
|
||||
#define bfd_mach_cpu32 8
|
||||
#define bfd_mach_mcf5200 9
|
||||
#define bfd_mach_mcf5206e 10
|
||||
#define bfd_mach_mcf5307 11
|
||||
#define bfd_mach_mcf5407 12
|
||||
#define bfd_mach_mcf528x 13
|
||||
#define bfd_mach_mcfv4e 14
|
||||
#define bfd_mach_mcf521x 15
|
||||
#define bfd_mach_mcf5249 16
|
||||
#define bfd_mach_mcf547x 17
|
||||
#define bfd_mach_mcf548x 18
|
||||
bfd_arch_vax, /* DEC Vax */
|
||||
bfd_arch_i960, /* Intel 960 */
|
||||
/* The order of the following is important.
|
||||
lower number indicates a machine type that
|
||||
only accepts a subset of the instructions
|
||||
available to machines with higher numbers.
|
||||
The exception is the "ca", which is
|
||||
incompatible with all other machines except
|
||||
"core". */
|
||||
|
||||
#define bfd_mach_i960_core 1
|
||||
#define bfd_mach_i960_ka_sa 2
|
||||
#define bfd_mach_i960_kb_sb 3
|
||||
#define bfd_mach_i960_mc 4
|
||||
#define bfd_mach_i960_xa 5
|
||||
#define bfd_mach_i960_ca 6
|
||||
#define bfd_mach_i960_jx 7
|
||||
#define bfd_mach_i960_hx 8
|
||||
|
||||
bfd_arch_a29k, /* AMD 29000 */
|
||||
bfd_arch_sparc, /* SPARC */
|
||||
#define bfd_mach_sparc 1
|
||||
/* The difference between v8plus and v9 is that v9 is a true 64 bit env. */
|
||||
#define bfd_mach_sparc_sparclet 2
|
||||
#define bfd_mach_sparc_sparclite 3
|
||||
#define bfd_mach_sparc_v8plus 4
|
||||
#define bfd_mach_sparc_v8plusa 5 /* with ultrasparc add'ns. */
|
||||
#define bfd_mach_sparc_sparclite_le 6
|
||||
#define bfd_mach_sparc_v9 7
|
||||
#define bfd_mach_sparc_v9a 8 /* with ultrasparc add'ns. */
|
||||
#define bfd_mach_sparc_v8plusb 9 /* with cheetah add'ns. */
|
||||
#define bfd_mach_sparc_v9b 10 /* with cheetah add'ns. */
|
||||
/* Nonzero if MACH has the v9 instruction set. */
|
||||
#define bfd_mach_sparc_v9_p(mach) \
|
||||
((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9b \
|
||||
&& (mach) != bfd_mach_sparc_sparclite_le)
|
||||
bfd_arch_mips, /* MIPS Rxxxx */
|
||||
#define bfd_mach_mips3000 3000
|
||||
#define bfd_mach_mips3900 3900
|
||||
#define bfd_mach_mips4000 4000
|
||||
#define bfd_mach_mips4010 4010
|
||||
#define bfd_mach_mips4100 4100
|
||||
#define bfd_mach_mips4300 4300
|
||||
#define bfd_mach_mips4400 4400
|
||||
#define bfd_mach_mips4600 4600
|
||||
#define bfd_mach_mips4650 4650
|
||||
#define bfd_mach_mips5000 5000
|
||||
#define bfd_mach_mips6000 6000
|
||||
#define bfd_mach_mips8000 8000
|
||||
#define bfd_mach_mips10000 10000
|
||||
#define bfd_mach_mips16 16
|
||||
bfd_arch_i386, /* Intel 386 */
|
||||
#define bfd_mach_i386_i386 0
|
||||
#define bfd_mach_i386_i8086 1
|
||||
#define bfd_mach_i386_i386_intel_syntax 2
|
||||
#define bfd_mach_x86_64 3
|
||||
#define bfd_mach_x86_64_intel_syntax 4
|
||||
bfd_arch_we32k, /* AT&T WE32xxx */
|
||||
bfd_arch_tahoe, /* CCI/Harris Tahoe */
|
||||
bfd_arch_i860, /* Intel 860 */
|
||||
bfd_arch_romp, /* IBM ROMP PC/RT */
|
||||
bfd_arch_alliant, /* Alliant */
|
||||
bfd_arch_convex, /* Convex */
|
||||
bfd_arch_m88k, /* Motorola 88xxx */
|
||||
bfd_arch_pyramid, /* Pyramid Technology */
|
||||
bfd_arch_h8300, /* Hitachi H8/300 */
|
||||
#define bfd_mach_h8300 1
|
||||
#define bfd_mach_h8300h 2
|
||||
#define bfd_mach_h8300s 3
|
||||
bfd_arch_powerpc, /* PowerPC */
|
||||
#define bfd_mach_ppc 0
|
||||
#define bfd_mach_ppc64 1
|
||||
#define bfd_mach_ppc_403 403
|
||||
#define bfd_mach_ppc_403gc 4030
|
||||
#define bfd_mach_ppc_505 505
|
||||
#define bfd_mach_ppc_601 601
|
||||
#define bfd_mach_ppc_602 602
|
||||
#define bfd_mach_ppc_603 603
|
||||
#define bfd_mach_ppc_ec603e 6031
|
||||
#define bfd_mach_ppc_604 604
|
||||
#define bfd_mach_ppc_620 620
|
||||
#define bfd_mach_ppc_630 630
|
||||
#define bfd_mach_ppc_750 750
|
||||
#define bfd_mach_ppc_860 860
|
||||
#define bfd_mach_ppc_a35 35
|
||||
#define bfd_mach_ppc_rs64ii 642
|
||||
#define bfd_mach_ppc_rs64iii 643
|
||||
#define bfd_mach_ppc_7400 7400
|
||||
bfd_arch_rs6000, /* IBM RS/6000 */
|
||||
bfd_arch_hppa, /* HP PA RISC */
|
||||
bfd_arch_d10v, /* Mitsubishi D10V */
|
||||
bfd_arch_z8k, /* Zilog Z8000 */
|
||||
#define bfd_mach_z8001 1
|
||||
#define bfd_mach_z8002 2
|
||||
bfd_arch_h8500, /* Hitachi H8/500 */
|
||||
bfd_arch_sh, /* Hitachi SH */
|
||||
#define bfd_mach_sh 1
|
||||
#define bfd_mach_sh2 0x20
|
||||
#define bfd_mach_sh_dsp 0x2d
|
||||
#define bfd_mach_sh2a 0x2a
|
||||
#define bfd_mach_sh2a_nofpu 0x2b
|
||||
#define bfd_mach_sh2e 0x2e
|
||||
#define bfd_mach_sh3 0x30
|
||||
#define bfd_mach_sh3_nommu 0x31
|
||||
#define bfd_mach_sh3_dsp 0x3d
|
||||
#define bfd_mach_sh3e 0x3e
|
||||
#define bfd_mach_sh4 0x40
|
||||
#define bfd_mach_sh4_nofpu 0x41
|
||||
#define bfd_mach_sh4_nommu_nofpu 0x42
|
||||
#define bfd_mach_sh4a 0x4a
|
||||
#define bfd_mach_sh4a_nofpu 0x4b
|
||||
#define bfd_mach_sh4al_dsp 0x4d
|
||||
#define bfd_mach_sh5 0x50
|
||||
bfd_arch_alpha, /* Dec Alpha */
|
||||
#define bfd_mach_alpha 1
|
||||
bfd_arch_arm, /* Advanced Risc Machines ARM */
|
||||
#define bfd_mach_arm_2 1
|
||||
#define bfd_mach_arm_2a 2
|
||||
#define bfd_mach_arm_3 3
|
||||
#define bfd_mach_arm_3M 4
|
||||
#define bfd_mach_arm_4 5
|
||||
#define bfd_mach_arm_4T 6
|
||||
bfd_arch_ns32k, /* National Semiconductors ns32000 */
|
||||
bfd_arch_w65, /* WDC 65816 */
|
||||
bfd_arch_tic30, /* Texas Instruments TMS320C30 */
|
||||
bfd_arch_v850, /* NEC V850 */
|
||||
#define bfd_mach_v850 0
|
||||
bfd_arch_arc, /* Argonaut RISC Core */
|
||||
#define bfd_mach_arc_base 0
|
||||
bfd_arch_m32r, /* Mitsubishi M32R/D */
|
||||
#define bfd_mach_m32r 0 /* backwards compatibility */
|
||||
bfd_arch_mn10200, /* Matsushita MN10200 */
|
||||
bfd_arch_mn10300, /* Matsushita MN10300 */
|
||||
bfd_arch_last
|
||||
};
|
||||
|
||||
typedef struct symbol_cache_entry
|
||||
{
|
||||
const char *name;
|
||||
union
|
||||
{
|
||||
PTR p;
|
||||
bfd_vma i;
|
||||
} udata;
|
||||
} asymbol;
|
||||
|
||||
typedef int (*fprintf_ftype) (void *, const char*, ...) ATTRIBUTE_FPTR_PRINTF_2;
|
||||
|
||||
enum dis_insn_type {
|
||||
dis_noninsn, /* Not a valid instruction */
|
||||
dis_nonbranch, /* Not a branch instruction */
|
||||
dis_branch, /* Unconditional branch */
|
||||
dis_condbranch, /* Conditional branch */
|
||||
dis_jsr, /* Jump to subroutine */
|
||||
dis_condjsr, /* Conditional jump to subroutine */
|
||||
dis_dref, /* Data reference instruction */
|
||||
dis_dref2 /* Two data references in instruction */
|
||||
};
|
||||
|
||||
/* This struct is passed into the instruction decoding routine,
|
||||
and is passed back out into each callback. The various fields are used
|
||||
for conveying information from your main routine into your callbacks,
|
||||
for passing information into the instruction decoders (such as the
|
||||
addresses of the callback functions), or for passing information
|
||||
back from the instruction decoders to their callers.
|
||||
|
||||
It must be initialized before it is first passed; this can be done
|
||||
by hand, or using one of the initialization macros below. */
|
||||
|
||||
typedef struct disassemble_info {
|
||||
fprintf_ftype fprintf_func;
|
||||
void *stream;
|
||||
void *application_data;
|
||||
|
||||
/* Target description. We could replace this with a pointer to the bfd,
|
||||
but that would require one. There currently isn't any such requirement
|
||||
so to avoid introducing one we record these explicitly. */
|
||||
/* The bfd_flavour. This can be bfd_target_unknown_flavour. */
|
||||
enum bfd_flavour flavour;
|
||||
/* The bfd_arch value. */
|
||||
enum bfd_architecture arch;
|
||||
/* The bfd_mach value. */
|
||||
unsigned long mach;
|
||||
/* Endianness (for bi-endian cpus). Mono-endian cpus can ignore this. */
|
||||
enum bfd_endian endian;
|
||||
/* An arch/mach-specific bitmask of selected instruction subsets, mainly
|
||||
for processors with run-time-switchable instruction sets. The default,
|
||||
zero, means that there is no constraint. CGEN-based opcodes ports
|
||||
may use ISA_foo masks. */
|
||||
void *insn_sets;
|
||||
|
||||
/* Some targets need information about the current section to accurately
|
||||
display insns. If this is NULL, the target disassembler function
|
||||
will have to make its best guess. */
|
||||
//asection *section;
|
||||
|
||||
/* An array of pointers to symbols either at the location being disassembled
|
||||
or at the start of the function being disassembled. The array is sorted
|
||||
so that the first symbol is intended to be the one used. The others are
|
||||
present for any misc. purposes. This is not set reliably, but if it is
|
||||
not NULL, it is correct. */
|
||||
asymbol **symbols;
|
||||
/* Number of symbols in array. */
|
||||
int num_symbols;
|
||||
|
||||
/* For use by the disassembler.
|
||||
The top 16 bits are reserved for public use (and are documented here).
|
||||
The bottom 16 bits are for the internal use of the disassembler. */
|
||||
unsigned long flags;
|
||||
#define INSN_HAS_RELOC 0x80000000
|
||||
void *private_data;
|
||||
|
||||
/* Function used to get bytes to disassemble. MEMADDR is the
|
||||
address of the stuff to be disassembled, MYADDR is the address to
|
||||
put the bytes in, and LENGTH is the number of bytes to read.
|
||||
INFO is a pointer to this struct.
|
||||
Returns an errno value or 0 for success. */
|
||||
int (*read_memory_func)
|
||||
(bfd_vma memaddr, bfd_byte *myaddr, unsigned int length,
|
||||
struct disassemble_info *info);
|
||||
|
||||
/* Function which should be called if we get an error that we can't
|
||||
recover from. STATUS is the errno value from read_memory_func and
|
||||
MEMADDR is the address that we were trying to read. INFO is a
|
||||
pointer to this struct. */
|
||||
void (*memory_error_func)
|
||||
(int status, bfd_vma memaddr, struct disassemble_info *info);
|
||||
|
||||
/* Function called to print ADDR. */
|
||||
void (*print_address_func)
|
||||
(bfd_vma addr, struct disassemble_info *info);
|
||||
|
||||
/* Function called to determine if there is a symbol at the given ADDR.
|
||||
If there is, the function returns 1, otherwise it returns 0.
|
||||
This is used by ports which support an overlay manager where
|
||||
the overlay number is held in the top part of an address. In
|
||||
some circumstances we want to include the overlay number in the
|
||||
address, (normally because there is a symbol associated with
|
||||
that address), but sometimes we want to mask out the overlay bits. */
|
||||
int (* symbol_at_address_func)
|
||||
(bfd_vma addr, struct disassemble_info * info);
|
||||
|
||||
/* Function called to check if a SYMBOL is can be displayed to the user.
|
||||
This is used by some ports that want to hide special symbols when
|
||||
displaying debugging outout. */
|
||||
bfd_boolean (* symbol_is_valid)
|
||||
(asymbol *, struct disassemble_info * info);
|
||||
|
||||
/* These are for buffer_read_memory. */
|
||||
bfd_byte *buffer;
|
||||
bfd_vma buffer_vma;
|
||||
unsigned int buffer_length;
|
||||
|
||||
/* This variable may be set by the instruction decoder. It suggests
|
||||
the number of bytes objdump should display on a single line. If
|
||||
the instruction decoder sets this, it should always set it to
|
||||
the same value in order to get reasonable looking output. */
|
||||
int bytes_per_line;
|
||||
|
||||
/* The next two variables control the way objdump displays the raw data. */
|
||||
/* For example, if bytes_per_line is 8 and bytes_per_chunk is 4, the */
|
||||
/* output will look like this:
|
||||
00: 00000000 00000000
|
||||
with the chunks displayed according to "display_endian". */
|
||||
int bytes_per_chunk;
|
||||
enum bfd_endian display_endian;
|
||||
|
||||
/* Number of octets per incremented target address
|
||||
Normally one, but some DSPs have byte sizes of 16 or 32 bits. */
|
||||
unsigned int octets_per_byte;
|
||||
|
||||
/* The number of zeroes we want to see at the end of a section before we
|
||||
start skipping them. */
|
||||
unsigned int skip_zeroes;
|
||||
|
||||
/* The number of zeroes to skip at the end of a section. If the number
|
||||
of zeroes at the end is between SKIP_ZEROES_AT_END and SKIP_ZEROES,
|
||||
they will be disassembled. If there are fewer than
|
||||
SKIP_ZEROES_AT_END, they will be skipped. This is a heuristic
|
||||
attempt to avoid disassembling zeroes inserted by section
|
||||
alignment. */
|
||||
unsigned int skip_zeroes_at_end;
|
||||
|
||||
/* Whether the disassembler always needs the relocations. */
|
||||
bfd_boolean disassembler_needs_relocs;
|
||||
|
||||
/* Results from instruction decoders. Not all decoders yet support
|
||||
this information. This info is set each time an instruction is
|
||||
decoded, and is only valid for the last such instruction.
|
||||
|
||||
To determine whether this decoder supports this information, set
|
||||
insn_info_valid to 0, decode an instruction, then check it. */
|
||||
|
||||
char insn_info_valid; /* Branch info has been set. */
|
||||
char branch_delay_insns; /* How many sequential insn's will run before
|
||||
a branch takes effect. (0 = normal) */
|
||||
char data_size; /* Size of data reference in insn, in bytes */
|
||||
enum dis_insn_type insn_type; /* Type of instruction */
|
||||
bfd_vma target; /* Target address of branch or dref, if known;
|
||||
zero if unknown. */
|
||||
bfd_vma target2; /* Second target address for dref2 */
|
||||
|
||||
/* Command line options specific to the target disassembler. */
|
||||
char * disassembler_options;
|
||||
|
||||
} disassemble_info;
|
||||
|
||||
|
||||
/* Standard disassemblers. Disassemble one instruction at the given
|
||||
target address. Return number of octets processed. */
|
||||
typedef int (*disassembler_ftype) (bfd_vma, disassemble_info *);
|
||||
|
||||
extern int print_insn_big_mips (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_little_mips (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_i386 (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_i386_att (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_i386_intel (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_ia64 (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_i370 (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_m68hc11 (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_m68hc12 (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_m68k (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_z80 (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_z8001 (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_z8002 (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_h8300 (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_h8300h (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_h8300s (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_h8500 (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_alpha (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_big_arm (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_little_arm (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_sparc (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_avr (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_bfin (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_d10v (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_d30v (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_dlx (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_fr30 (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_hppa (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_i860 (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_i960 (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_ip2k (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_m32r (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_m88k (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_maxq_little (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_maxq_big (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_mcore (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_mmix (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_mn10200 (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_mn10300 (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_mt (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_msp430 (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_ns32k (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_crx (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_openrisc (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_big_or32 (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_little_or32 (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_pdp11 (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_pj (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_big_powerpc (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_little_powerpc (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_rs6000 (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_s390 (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_sh (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_tic30 (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_tic4x (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_tic54x (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_tic80 (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_v850 (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_vax (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_w65 (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_xstormy16 (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_xtensa (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_sh64 (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_sh64x_media (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_frv (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_iq2000 (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_xc16x (bfd_vma, disassemble_info *);
|
||||
extern int print_insn_m32c (bfd_vma, disassemble_info *);
|
||||
|
||||
extern disassembler_ftype arc_get_disassembler (void *);
|
||||
//extern disassembler_ftype cris_get_disassembler (bfd *);
|
||||
|
||||
extern void print_mips_disassembler_options (FILE *);
|
||||
extern void print_ppc_disassembler_options (FILE *);
|
||||
extern void print_arm_disassembler_options (FILE *);
|
||||
extern void parse_arm_disassembler_option (char *);
|
||||
extern int get_arm_regname_num_options (void);
|
||||
extern int set_arm_regname_option (int);
|
||||
extern int get_arm_regnames (int, const char **, const char **, const char *const **);
|
||||
extern bfd_boolean arm_symbol_is_valid (asymbol *, struct disassemble_info *);
|
||||
|
||||
/* Fetch the disassembler for a given BFD, if that support is available. */
|
||||
//extern disassembler_ftype disassembler (bfd *);
|
||||
|
||||
/* Amend the disassemble_info structure as necessary for the target architecture.
|
||||
Should only be called after initialising the info->arch field. */
|
||||
extern void disassemble_init_for_target (struct disassemble_info * info);
|
||||
|
||||
/* Document any target specific options available from the disassembler. */
|
||||
extern void disassembler_usage (FILE *);
|
||||
|
||||
|
||||
/* This block of definitions is for particular callers who read instructions
|
||||
into a buffer before calling the instruction decoder. */
|
||||
|
||||
/* Here is a function which callers may wish to use for read_memory_func.
|
||||
It gets bytes from a buffer. */
|
||||
extern int buffer_read_memory
|
||||
(bfd_vma, bfd_byte *, unsigned int, struct disassemble_info *);
|
||||
|
||||
/* This function goes with buffer_read_memory.
|
||||
It prints a message using info->fprintf_func and info->stream. */
|
||||
extern void perror_memory (int, bfd_vma, struct disassemble_info *);
|
||||
|
||||
|
||||
/* Just print the address in hex. This is included for completeness even
|
||||
though both GDB and objdump provide their own (to print symbolic
|
||||
addresses). */
|
||||
extern void generic_print_address
|
||||
(bfd_vma, struct disassemble_info *);
|
||||
|
||||
/* Always true. */
|
||||
extern int generic_symbol_at_address
|
||||
(bfd_vma, struct disassemble_info *);
|
||||
|
||||
/* Also always true. */
|
||||
extern bfd_boolean generic_symbol_is_valid
|
||||
(asymbol *, struct disassemble_info *);
|
||||
|
||||
/* Method to initialize a disassemble_info struct. This should be
|
||||
called by all applications creating such a struct. */
|
||||
extern void init_disassemble_info (struct disassemble_info *info, void *stream,
|
||||
fprintf_ftype fprintf_func);
|
||||
|
||||
/* For compatibility with existing code. */
|
||||
#define INIT_DISASSEMBLE_INFO(INFO, STREAM, FPRINTF_FUNC) \
|
||||
init_disassemble_info (&(INFO), (STREAM), (fprintf_ftype) (FPRINTF_FUNC))
|
||||
#define INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC) \
|
||||
init_disassemble_info (&(INFO), (STREAM), (fprintf_ftype) (FPRINTF_FUNC))
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ! defined (DIS_ASM_H) */
|
||||
File diff suppressed because it is too large.
Load diff
@@ -1,148 +0,0 @@
|
||||
/* ia64-asmtab.h -- Header for compacted IA-64 opcode tables.
|
||||
Copyright 1999, 2000 Free Software Foundation, Inc.
|
||||
Contributed by Bob Manson of Cygnus Support <manson@cygnus.com>
|
||||
|
||||
This file is part of GDB, GAS, and the GNU binutils.
|
||||
|
||||
GDB, GAS, and the GNU binutils are free software; you can redistribute
|
||||
them and/or modify them under the terms of the GNU General Public
|
||||
License as published by the Free Software Foundation; either version
|
||||
2, or (at your option) any later version.
|
||||
|
||||
GDB, GAS, and the GNU binutils are distributed in the hope that they
|
||||
will be useful, but WITHOUT ANY WARRANTY; without even the implied
|
||||
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
|
||||
the GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this file; see the file COPYING. If not, write to the
|
||||
Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
|
||||
02110-1301, USA. */
|
||||
|
||||
#ifndef IA64_ASMTAB_H
|
||||
#define IA64_ASMTAB_H
|
||||
|
||||
#include "ia64.h"
|
||||
|
||||
/* The primary opcode table is made up of the following: */
|
||||
struct ia64_main_table
|
||||
{
|
||||
/* The entry in the string table that corresponds to the name of this
|
||||
opcode. */
|
||||
unsigned short name_index;
|
||||
|
||||
/* The type of opcode; corresponds to the TYPE field in
|
||||
struct ia64_opcode. */
|
||||
unsigned char opcode_type;
|
||||
|
||||
/* The number of outputs for this opcode. */
|
||||
unsigned char num_outputs;
|
||||
|
||||
/* The base insn value for this opcode. It may be modified by completers. */
|
||||
ia64_insn opcode;
|
||||
|
||||
/* The mask of valid bits in OPCODE. Zeros indicate operand fields. */
|
||||
ia64_insn mask;
|
||||
|
||||
/* The operands of this instruction. Corresponds to the OPERANDS field
|
||||
in struct ia64_opcode. */
|
||||
unsigned char operands[5];
|
||||
|
||||
/* The flags for this instruction. Corresponds to the FLAGS field in
|
||||
struct ia64_opcode. */
|
||||
short flags;
|
||||
|
||||
/* The tree of completers for this instruction; this is an offset into
|
||||
completer_table. */
|
||||
short completers;
|
||||
};
|
||||
|
||||
/* Each instruction has a set of possible "completers", or additional
|
||||
suffixes that can alter the instruction's behavior, and which has
|
||||
potentially different dependencies.
|
||||
|
||||
The completer entries modify certain bits in the instruction opcode.
|
||||
Which bits are to be modified are marked by the BITS, MASK and
|
||||
OFFSET fields. The completer entry may also note dependencies for the
|
||||
opcode.
|
||||
|
||||
These completers are arranged in a DAG; the pointers are indexes
|
||||
into the completer_table array. The completer DAG is searched by
|
||||
find_completer () and ia64_find_matching_opcode ().
|
||||
|
||||
Note that each completer needs to be applied in turn, so that if we
|
||||
have the instruction
|
||||
cmp.lt.unc
|
||||
the completer entries for both "lt" and "unc" would need to be applied
|
||||
to the opcode's value.
|
||||
|
||||
Some instructions do not require any completers; these contain an
|
||||
empty completer entry. Instructions that require a completer do
|
||||
not contain an empty entry.
|
||||
|
||||
Terminal completers (those completers that validly complete an
|
||||
instruction) are marked by having the TERMINAL_COMPLETER flag set.
|
||||
|
||||
Only dependencies listed in the terminal completer for an opcode are
|
||||
considered to apply to that opcode instance. */
|
||||
|
||||
struct ia64_completer_table
|
||||
{
|
||||
/* The bit value that this completer sets. */
|
||||
unsigned int bits;
|
||||
|
||||
/* And its mask. 1s are bits that are to be modified in the
|
||||
instruction. */
|
||||
unsigned int mask;
|
||||
|
||||
/* The entry in the string table that corresponds to the name of this
|
||||
completer. */
|
||||
unsigned short name_index;
|
||||
|
||||
/* An alternative completer, or -1 if this is the end of the chain. */
|
||||
short alternative;
|
||||
|
||||
/* A pointer to the DAG of completers that can potentially follow
|
||||
this one, or -1. */
|
||||
short subentries;
|
||||
|
||||
/* The bit offset in the instruction where BITS and MASK should be
|
||||
applied. */
|
||||
unsigned char offset : 7;
|
||||
|
||||
unsigned char terminal_completer : 1;
|
||||
|
||||
/* Index into the dependency list table */
|
||||
short dependencies;
|
||||
};
|
||||
|
||||
/* This contains sufficient information for the disassembler to resolve
|
||||
the complete name of the original instruction. */
|
||||
struct ia64_dis_names
|
||||
{
|
||||
/* COMPLETER_INDEX represents the tree of completers that make up
|
||||
the instruction. The LSB represents the top of the tree for the
|
||||
specified instruction.
|
||||
|
||||
A 0 bit indicates to go to the next alternate completer via the
|
||||
alternative field; a 1 bit indicates that the current completer
|
||||
is part of the instruction, and to go down the subentries index.
|
||||
We know we've reached the final completer when we run out of 1
|
||||
bits.
|
||||
|
||||
There is always at least one 1 bit. */
|
||||
unsigned int completer_index : 20;
|
||||
|
||||
/* The index in the main_table[] array for the instruction. */
|
||||
unsigned short insn_index : 11;
|
||||
|
||||
/* If set, the next entry in this table is an alternate possibility
|
||||
for this instruction encoding. Which one to use is determined by
|
||||
the instruction type and other factors (see opcode_verify ()). */
|
||||
unsigned int next_flag : 1;
|
||||
|
||||
/* The disassembly priority of this entry among instructions. */
|
||||
unsigned short priority;
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -1,309 +0,0 @@
|
||||
/* ia64-dis.c -- Disassemble ia64 instructions
|
||||
Copyright 1998, 1999, 2000, 2002 Free Software Foundation, Inc.
|
||||
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
|
||||
|
||||
This file is part of GDB, GAS, and the GNU binutils.
|
||||
|
||||
GDB, GAS, and the GNU binutils are free software; you can redistribute
|
||||
them and/or modify them under the terms of the GNU General Public
|
||||
License as published by the Free Software Foundation; either version
|
||||
2, or (at your option) any later version.
|
||||
|
||||
GDB, GAS, and the GNU binutils are distributed in the hope that they
|
||||
will be useful, but WITHOUT ANY WARRANTY; without even the implied
|
||||
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
|
||||
the GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this file; see the file COPYING. If not, write to the
|
||||
Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
|
||||
02110-1301, USA. */
|
||||
|
||||
#include <assert.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "dis-asm.h"
|
||||
#include "ia64.h"
|
||||
|
||||
#define NELEMS(a) ((int) (sizeof (a) / sizeof (a[0])))
|
||||
|
||||
/* Disassemble ia64 instruction. */
|
||||
|
||||
/* Return the instruction type for OPCODE found in unit UNIT. */
|
||||
|
||||
static enum ia64_insn_type
|
||||
unit_to_type (ia64_insn opcode, enum ia64_unit unit)
|
||||
{
|
||||
enum ia64_insn_type type;
|
||||
int op;
|
||||
|
||||
op = IA64_OP (opcode);
|
||||
|
||||
if (op >= 8 && (unit == IA64_UNIT_I || unit == IA64_UNIT_M))
|
||||
{
|
||||
type = IA64_TYPE_A;
|
||||
}
|
||||
else
|
||||
{
|
||||
switch (unit)
|
||||
{
|
||||
case IA64_UNIT_I:
|
||||
type = IA64_TYPE_I; break;
|
||||
case IA64_UNIT_M:
|
||||
type = IA64_TYPE_M; break;
|
||||
case IA64_UNIT_B:
|
||||
type = IA64_TYPE_B; break;
|
||||
case IA64_UNIT_F:
|
||||
type = IA64_TYPE_F; break;
|
||||
case IA64_UNIT_L:
|
||||
case IA64_UNIT_X:
|
||||
type = IA64_TYPE_X; break;
|
||||
default:
|
||||
type = -1;
|
||||
}
|
||||
}
|
||||
return type;
|
||||
}
|
||||
|
||||
int
|
||||
print_insn_ia64 (bfd_vma memaddr, struct disassemble_info *info)
|
||||
{
|
||||
ia64_insn t0, t1, slot[3], template, s_bit, insn;
|
||||
int slotnum, j, status, need_comma, retval, slot_multiplier;
|
||||
const struct ia64_operand *odesc;
|
||||
const struct ia64_opcode *idesc;
|
||||
const char *err, *str, *tname;
|
||||
BFD_HOST_U_64_BIT value;
|
||||
bfd_byte bundle[16];
|
||||
enum ia64_unit unit;
|
||||
char regname[16];
|
||||
|
||||
if (info->bytes_per_line == 0)
|
||||
info->bytes_per_line = 6;
|
||||
info->display_endian = info->endian;
|
||||
|
||||
slot_multiplier = info->bytes_per_line;
|
||||
retval = slot_multiplier;
|
||||
|
||||
slotnum = (((long) memaddr) & 0xf) / slot_multiplier;
|
||||
if (slotnum > 2)
|
||||
return -1;
|
||||
|
||||
memaddr -= (memaddr & 0xf);
|
||||
status = (*info->read_memory_func) (memaddr, bundle, sizeof (bundle), info);
|
||||
if (status != 0)
|
||||
{
|
||||
(*info->memory_error_func) (status, memaddr, info);
|
||||
return -1;
|
||||
}
|
||||
/* bundles are always in little-endian byte order */
|
||||
t0 = bfd_getl64 (bundle);
|
||||
t1 = bfd_getl64 (bundle + 8);
|
||||
s_bit = t0 & 1;
|
||||
template = (t0 >> 1) & 0xf;
|
||||
slot[0] = (t0 >> 5) & 0x1ffffffffffLL;
|
||||
slot[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18);
|
||||
slot[2] = (t1 >> 23) & 0x1ffffffffffLL;
|
||||
|
||||
tname = ia64_templ_desc[template].name;
|
||||
if (slotnum == 0)
|
||||
(*info->fprintf_func) (info->stream, "[%s] ", tname);
|
||||
else
|
||||
(*info->fprintf_func) (info->stream, " ");
|
||||
|
||||
unit = ia64_templ_desc[template].exec_unit[slotnum];
|
||||
|
||||
if (template == 2 && slotnum == 1)
|
||||
{
|
||||
/* skip L slot in MLI template: */
|
||||
slotnum = 2;
|
||||
retval += slot_multiplier;
|
||||
}
|
||||
|
||||
insn = slot[slotnum];
|
||||
|
||||
if (unit == IA64_UNIT_NIL)
|
||||
goto decoding_failed;
|
||||
|
||||
idesc = ia64_dis_opcode (insn, unit_to_type (insn, unit));
|
||||
if (idesc == NULL)
|
||||
goto decoding_failed;
|
||||
|
||||
/* print predicate, if any: */
|
||||
|
||||
if ((idesc->flags & IA64_OPCODE_NO_PRED)
|
||||
|| (insn & 0x3f) == 0)
|
||||
(*info->fprintf_func) (info->stream, " ");
|
||||
else
|
||||
(*info->fprintf_func) (info->stream, "(p%02d) ", (int)(insn & 0x3f));
|
||||
|
||||
/* now the actual instruction: */
|
||||
|
||||
(*info->fprintf_func) (info->stream, "%s", idesc->name);
|
||||
if (idesc->operands[0])
|
||||
(*info->fprintf_func) (info->stream, " ");
|
||||
|
||||
need_comma = 0;
|
||||
for (j = 0; j < NELEMS (idesc->operands) && idesc->operands[j]; ++j)
|
||||
{
|
||||
odesc = elf64_ia64_operands + idesc->operands[j];
|
||||
|
||||
if (need_comma)
|
||||
(*info->fprintf_func) (info->stream, ",");
|
||||
|
||||
if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64)
|
||||
{
|
||||
/* special case of 64 bit immediate load: */
|
||||
value = ((insn >> 13) & 0x7f) | (((insn >> 27) & 0x1ff) << 7)
|
||||
| (((insn >> 22) & 0x1f) << 16) | (((insn >> 21) & 0x1) << 21)
|
||||
| (slot[1] << 22) | (((insn >> 36) & 0x1) << 63);
|
||||
}
|
||||
else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62)
|
||||
{
|
||||
/* 62-bit immediate for nop.x/break.x */
|
||||
value = ((slot[1] & 0x1ffffffffffLL) << 21)
|
||||
| (((insn >> 36) & 0x1) << 20)
|
||||
| ((insn >> 6) & 0xfffff);
|
||||
}
|
||||
else if (odesc - elf64_ia64_operands == IA64_OPND_TGT64)
|
||||
{
|
||||
/* 60-bit immediate for long branches. */
|
||||
value = (((insn >> 13) & 0xfffff)
|
||||
| (((insn >> 36) & 1) << 59)
|
||||
| (((slot[1] >> 2) & 0x7fffffffffLL) << 20)) << 4;
|
||||
}
|
||||
else
|
||||
{
|
||||
err = (*odesc->extract) (odesc, insn, &value);
|
||||
if (err)
|
||||
{
|
||||
(*info->fprintf_func) (info->stream, "%s", err);
|
||||
goto done;
|
||||
}
|
||||
}
|
||||
|
||||
switch (odesc->class)
|
||||
{
|
||||
case IA64_OPND_CLASS_CST:
|
||||
(*info->fprintf_func) (info->stream, "%s", odesc->str);
|
||||
break;
|
||||
|
||||
case IA64_OPND_CLASS_REG:
|
||||
if (odesc->str[0] == 'a' && odesc->str[1] == 'r')
|
||||
{
|
||||
switch (value)
|
||||
{
|
||||
case 0: case 1: case 2: case 3:
|
||||
case 4: case 5: case 6: case 7:
|
||||
sprintf (regname, "ar.k%u", (unsigned int) value);
|
||||
break;
|
||||
case 16: strcpy (regname, "ar.rsc"); break;
|
||||
case 17: strcpy (regname, "ar.bsp"); break;
|
||||
case 18: strcpy (regname, "ar.bspstore"); break;
|
||||
case 19: strcpy (regname, "ar.rnat"); break;
|
||||
case 32: strcpy (regname, "ar.ccv"); break;
|
||||
case 36: strcpy (regname, "ar.unat"); break;
|
||||
case 40: strcpy (regname, "ar.fpsr"); break;
|
||||
case 44: strcpy (regname, "ar.itc"); break;
|
||||
case 64: strcpy (regname, "ar.pfs"); break;
|
||||
case 65: strcpy (regname, "ar.lc"); break;
|
||||
case 66: strcpy (regname, "ar.ec"); break;
|
||||
default:
|
||||
sprintf (regname, "ar%u", (unsigned int) value);
|
||||
break;
|
||||
}
|
||||
(*info->fprintf_func) (info->stream, "%s", regname);
|
||||
}
|
||||
else if (odesc->str[0] == 'c' && odesc->str[1] == 'r')
|
||||
{
|
||||
switch (value)
|
||||
{
|
||||
case 0: strcpy (regname, "cr.dcr"); break;
|
||||
case 1: strcpy (regname, "cr.itm"); break;
|
||||
case 2: strcpy (regname, "cr.iva"); break;
|
||||
case 8: strcpy (regname, "cr.pta"); break;
|
||||
case 16: strcpy (regname, "cr.ipsr"); break;
|
||||
case 17: strcpy (regname, "cr.isr"); break;
|
||||
case 19: strcpy (regname, "cr.iip"); break;
|
||||
case 20: strcpy (regname, "cr.ifa"); break;
|
||||
case 21: strcpy (regname, "cr.itir"); break;
|
||||
case 22: strcpy (regname, "cr.iipa"); break;
|
||||
case 23: strcpy (regname, "cr.ifs"); break;
|
||||
case 24: strcpy (regname, "cr.iim"); break;
|
||||
case 25: strcpy (regname, "cr.iha"); break;
|
||||
case 64: strcpy (regname, "cr.lid"); break;
|
||||
case 65: strcpy (regname, "cr.ivr"); break;
|
||||
case 66: strcpy (regname, "cr.tpr"); break;
|
||||
case 67: strcpy (regname, "cr.eoi"); break;
|
||||
case 68: strcpy (regname, "cr.irr0"); break;
|
||||
case 69: strcpy (regname, "cr.irr1"); break;
|
||||
case 70: strcpy (regname, "cr.irr2"); break;
|
||||
case 71: strcpy (regname, "cr.irr3"); break;
|
||||
case 72: strcpy (regname, "cr.itv"); break;
|
||||
case 73: strcpy (regname, "cr.pmv"); break;
|
||||
case 74: strcpy (regname, "cr.cmcv"); break;
|
||||
case 80: strcpy (regname, "cr.lrr0"); break;
|
||||
case 81: strcpy (regname, "cr.lrr1"); break;
|
||||
default:
|
||||
sprintf (regname, "cr%u", (unsigned int) value);
|
||||
break;
|
||||
}
|
||||
(*info->fprintf_func) (info->stream, "%s", regname);
|
||||
}
|
||||
else
|
||||
(*info->fprintf_func) (info->stream, "%s%d", odesc->str, (int)value);
|
||||
break;
|
||||
|
||||
case IA64_OPND_CLASS_IND:
|
||||
(*info->fprintf_func) (info->stream, "%s[r%d]", odesc->str, (int)value);
|
||||
break;
|
||||
|
||||
case IA64_OPND_CLASS_ABS:
|
||||
str = 0;
|
||||
if (odesc - elf64_ia64_operands == IA64_OPND_MBTYPE4)
|
||||
switch (value)
|
||||
{
|
||||
case 0x0: str = "@brcst"; break;
|
||||
case 0x8: str = "@mix"; break;
|
||||
case 0x9: str = "@shuf"; break;
|
||||
case 0xa: str = "@alt"; break;
|
||||
case 0xb: str = "@rev"; break;
|
||||
}
|
||||
|
||||
if (str)
|
||||
(*info->fprintf_func) (info->stream, "%s", str);
|
||||
else if (odesc->flags & IA64_OPND_FLAG_DECIMAL_SIGNED)
|
||||
(*info->fprintf_func) (info->stream, "%lld", (long long) value);
|
||||
else if (odesc->flags & IA64_OPND_FLAG_DECIMAL_UNSIGNED)
|
||||
(*info->fprintf_func) (info->stream, "%llu", (long long) value);
|
||||
else
|
||||
(*info->fprintf_func) (info->stream, "0x%llx", (long long) value);
|
||||
break;
|
||||
|
||||
case IA64_OPND_CLASS_REL:
|
||||
(*info->print_address_func) (memaddr + value, info);
|
||||
break;
|
||||
}
|
||||
|
||||
need_comma = 1;
|
||||
if (j + 1 == idesc->num_outputs)
|
||||
{
|
||||
(*info->fprintf_func) (info->stream, "=");
|
||||
need_comma = 0;
|
||||
}
|
||||
}
|
||||
if (slotnum + 1 == ia64_templ_desc[template].group_boundary
|
||||
|| ((slotnum == 2) && s_bit))
|
||||
(*info->fprintf_func) (info->stream, ";;");
|
||||
|
||||
done:
|
||||
ia64_free_opcode ((struct ia64_opcode *)idesc);
|
||||
failed:
|
||||
if (slotnum == 2)
|
||||
retval += 16 - 3*slot_multiplier;
|
||||
return retval;
|
||||
|
||||
decoding_failed:
|
||||
(*info->fprintf_func) (info->stream, " data8 %#011llx", (long long) insn);
|
||||
goto failed;
|
||||
}
|
||||
File diff suppressed because it is too large.
Load diff
@@ -1,419 +0,0 @@
|
||||
/* ia64-opc-a.c -- IA-64 `A' opcode table.
|
||||
Copyright 1998, 1999, 2000, 2001, 2002, 2004
|
||||
Free Software Foundation, Inc.
|
||||
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
|
||||
|
||||
This file is part of GDB, GAS, and the GNU binutils.
|
||||
|
||||
GDB, GAS, and the GNU binutils are free software; you can redistribute
|
||||
them and/or modify them under the terms of the GNU General Public
|
||||
License as published by the Free Software Foundation; either version
|
||||
2, or (at your option) any later version.
|
||||
|
||||
GDB, GAS, and the GNU binutils are distributed in the hope that they
|
||||
will be useful, but WITHOUT ANY WARRANTY; without even the implied
|
||||
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
|
||||
the GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this file; see the file COPYING. If not, write to the
|
||||
Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
|
||||
02110-1301, USA. */
|
||||
|
||||
#include "ia64-opc.h"
|
||||
|
||||
#define A IA64_TYPE_A, 1
|
||||
#define A2 IA64_TYPE_A, 2
|
||||
|
||||
/* instruction bit fields: */
|
||||
#define bC(x) (((ia64_insn) ((x) & 0x1)) << 12)
|
||||
#define bImm14(x) ((((ia64_insn) (((x) >> 0) & 0x7f)) << 13) | \
|
||||
(((ia64_insn) (((x) >> 7) & 0x3f)) << 27) | \
|
||||
(((ia64_insn) (((x) >> 13) & 0x01)) << 36))
|
||||
#define bR3a(x) (((ia64_insn) ((x) & 0x7f)) << 20)
|
||||
#define bR3b(x) (((ia64_insn) ((x) & 0x3)) << 20)
|
||||
#define bTa(x) (((ia64_insn) ((x) & 0x1)) << 33)
|
||||
#define bTb(x) (((ia64_insn) ((x) & 0x1)) << 36)
|
||||
#define bVe(x) (((ia64_insn) ((x) & 0x1)) << 33)
|
||||
#define bX(x) (((ia64_insn) ((x) & 0x1)) << 33)
|
||||
#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 34)
|
||||
#define bX2a(x) (((ia64_insn) ((x) & 0x3)) << 34)
|
||||
#define bX2b(x) (((ia64_insn) ((x) & 0x3)) << 27)
|
||||
#define bX4(x) (((ia64_insn) ((x) & 0xf)) << 29)
|
||||
#define bZa(x) (((ia64_insn) ((x) & 0x1)) << 36)
|
||||
#define bZb(x) (((ia64_insn) ((x) & 0x1)) << 33)
|
||||
|
||||
/* instruction bit masks: */
|
||||
#define mC bC (-1)
|
||||
#define mImm14 bImm14 (-1)
|
||||
#define mR3a bR3a (-1)
|
||||
#define mR3b bR3b (-1)
|
||||
#define mTa bTa (-1)
|
||||
#define mTb bTb (-1)
|
||||
#define mVe bVe (-1)
|
||||
#define mX bX (-1)
|
||||
#define mX2 bX2 (-1)
|
||||
#define mX2a bX2a (-1)
|
||||
#define mX2b bX2b (-1)
|
||||
#define mX4 bX4 (-1)
|
||||
#define mZa bZa (-1)
|
||||
#define mZb bZb (-1)
|
||||
|
||||
#define OpR3b(a,b) (bOp (a) | bR3b (b)), (mOp | mR3b)
|
||||
#define OpX2aVe(a,b,c) (bOp (a) | bX2a (b) | bVe (c)), \
|
||||
(mOp | mX2a | mVe)
|
||||
#define OpX2aVeR3a(a,b,c,d) (bOp (a) | bX2a (b) | bVe (c) | bR3a (d)), \
|
||||
(mOp | mX2a | mVe | mR3a)
|
||||
#define OpX2aVeImm14(a,b,c,d) (bOp (a) | bX2a (b) | bVe (c) | bImm14 (d)), \
|
||||
(mOp | mX2a | mVe | mImm14)
|
||||
#define OpX2aVeX4(a,b,c,d) (bOp (a) | bX2a (b) | bVe (c) | bX4 (d)), \
|
||||
(mOp | mX2a | mVe | mX4)
|
||||
#define OpX2aVeX4X2b(a,b,c,d,e) \
|
||||
(bOp (a) | bX2a (b) | bVe (c) | bX4 (d) | bX2b (e)), \
|
||||
(mOp | mX2a | mVe | mX4 | mX2b)
|
||||
#define OpX2TbTaC(a,b,c,d,e) \
|
||||
(bOp (a) | bX2 (b) | bTb (c) | bTa (d) | bC (e)), \
|
||||
(mOp | mX2 | mTb | mTa | mC)
|
||||
#define OpX2TaC(a,b,c,d) (bOp (a) | bX2 (b) | bTa (c) | bC (d)), \
|
||||
(mOp | mX2 | mTa | mC)
|
||||
#define OpX2aZaZbX4(a,b,c,d,e) \
|
||||
(bOp (a) | bX2a (b) | bZa (c) | bZb (d) | bX4 (e)), \
|
||||
(mOp | mX2a | mZa | mZb | mX4)
|
||||
#define OpX2aZaZbX4X2b(a,b,c,d,e,f) \
|
||||
(bOp (a) | bX2a (b) | bZa (c) | bZb (d) | bX4 (e) | bX2b (f)), \
|
||||
(mOp | mX2a | mZa | mZb | mX4 | mX2b)
|
||||
|
||||
/* Used to initialise unused fields in ia64_opcode struct,
|
||||
in order to stop gcc from complaining. */
|
||||
#define EMPTY 0,0,NULL
|
||||
|
||||
struct ia64_opcode ia64_opcodes_a[] =
|
||||
{
|
||||
/* A-type instruction encodings (sorted according to major opcode). */
|
||||
|
||||
{"add", A, OpX2aVeX4X2b (8, 0, 0, 0, 0), {R1, R2, R3}, EMPTY},
|
||||
{"add", A, OpX2aVeX4X2b (8, 0, 0, 0, 1), {R1, R2, R3, C1}, EMPTY},
|
||||
{"sub", A, OpX2aVeX4X2b (8, 0, 0, 1, 1), {R1, R2, R3}, EMPTY},
|
||||
{"sub", A, OpX2aVeX4X2b (8, 0, 0, 1, 0), {R1, R2, R3, C1}, EMPTY},
|
||||
{"addp4", A, OpX2aVeX4X2b (8, 0, 0, 2, 0), {R1, R2, R3}, EMPTY},
|
||||
{"and", A, OpX2aVeX4X2b (8, 0, 0, 3, 0), {R1, R2, R3}, EMPTY},
|
||||
{"andcm", A, OpX2aVeX4X2b (8, 0, 0, 3, 1), {R1, R2, R3}, EMPTY},
|
||||
{"or", A, OpX2aVeX4X2b (8, 0, 0, 3, 2), {R1, R2, R3}, EMPTY},
|
||||
{"xor", A, OpX2aVeX4X2b (8, 0, 0, 3, 3), {R1, R2, R3}, EMPTY},
|
||||
{"shladd", A, OpX2aVeX4 (8, 0, 0, 4), {R1, R2, CNT2a, R3}, EMPTY},
|
||||
{"shladdp4", A, OpX2aVeX4 (8, 0, 0, 6), {R1, R2, CNT2a, R3}, EMPTY},
|
||||
{"sub", A, OpX2aVeX4X2b (8, 0, 0, 9, 1), {R1, IMM8, R3}, EMPTY},
|
||||
{"and", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 0), {R1, IMM8, R3}, EMPTY},
|
||||
{"andcm", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 1), {R1, IMM8, R3}, EMPTY},
|
||||
{"or", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 2), {R1, IMM8, R3}, EMPTY},
|
||||
{"xor", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 3), {R1, IMM8, R3}, EMPTY},
|
||||
{"mov", A, OpX2aVeImm14 (8, 2, 0, 0), {R1, R3}, EMPTY},
|
||||
/* A mov immediate pseudo for adds was deleted. It failed for immediate
|
||||
operands requiring relocs, e.g. @pltoff(a). */
|
||||
{"adds", A, OpX2aVe (8, 2, 0), {R1, IMM14, R3}, EMPTY},
|
||||
{"addp4", A, OpX2aVe (8, 3, 0), {R1, IMM14, R3}, EMPTY},
|
||||
{"padd1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 0), {R1, R2, R3}, EMPTY},
|
||||
{"padd2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 0), {R1, R2, R3}, EMPTY},
|
||||
{"padd4", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 0, 0), {R1, R2, R3}, EMPTY},
|
||||
{"padd1.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 1), {R1, R2, R3}, EMPTY},
|
||||
{"padd2.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 1), {R1, R2, R3}, EMPTY},
|
||||
{"padd1.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 2), {R1, R2, R3}, EMPTY},
|
||||
{"padd2.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 2), {R1, R2, R3}, EMPTY},
|
||||
{"padd1.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 3), {R1, R2, R3}, EMPTY},
|
||||
{"padd2.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 3), {R1, R2, R3}, EMPTY},
|
||||
{"psub1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 0), {R1, R2, R3}, EMPTY},
|
||||
{"psub2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 0), {R1, R2, R3}, EMPTY},
|
||||
{"psub4", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 1, 0), {R1, R2, R3}, EMPTY},
|
||||
{"psub1.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 1), {R1, R2, R3}, EMPTY},
|
||||
{"psub2.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 1), {R1, R2, R3}, EMPTY},
|
||||
{"psub1.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 2), {R1, R2, R3}, EMPTY},
|
||||
{"psub2.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 2), {R1, R2, R3}, EMPTY},
|
||||
{"psub1.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 3), {R1, R2, R3}, EMPTY},
|
||||
{"psub2.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 3), {R1, R2, R3}, EMPTY},
|
||||
{"pavg1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 2, 2), {R1, R2, R3}, EMPTY},
|
||||
{"pavg2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 2, 2), {R1, R2, R3}, EMPTY},
|
||||
{"pavg1.raz", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 2, 3), {R1, R2, R3}, EMPTY},
|
||||
{"pavg2.raz", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 2, 3), {R1, R2, R3}, EMPTY},
|
||||
{"pavgsub1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 3, 2), {R1, R2, R3}, EMPTY},
|
||||
{"pavgsub2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 3, 2), {R1, R2, R3}, EMPTY},
|
||||
{"pcmp1.eq", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 9, 0), {R1, R2, R3}, EMPTY},
|
||||
{"pcmp2.eq", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 9, 0), {R1, R2, R3}, EMPTY},
|
||||
{"pcmp4.eq", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 9, 0), {R1, R2, R3}, EMPTY},
|
||||
{"pcmp1.gt", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 9, 1), {R1, R2, R3}, EMPTY},
|
||||
{"pcmp2.gt", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 9, 1), {R1, R2, R3}, EMPTY},
|
||||
{"pcmp4.gt", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 9, 1), {R1, R2, R3}, EMPTY},
|
||||
{"pshladd2", A, OpX2aZaZbX4 (8, 1, 0, 1, 4), {R1, R2, CNT2b, R3}, EMPTY},
|
||||
{"pshradd2", A, OpX2aZaZbX4 (8, 1, 0, 1, 6), {R1, R2, CNT2b, R3}, EMPTY},
|
||||
|
||||
{"mov", A, OpR3b (9, 0), {R1, IMM22}, PSEUDO, 0, NULL},
|
||||
{"addl", A, Op (9), {R1, IMM22, R3_2}, EMPTY},
|
||||
|
||||
{"cmp.lt", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R2, R3}, EMPTY},
|
||||
{"cmp.le", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R3, R2}, EMPTY},
|
||||
{"cmp.gt", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R3, R2}, EMPTY},
|
||||
{"cmp.ge", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R2, R3}, EMPTY},
|
||||
{"cmp.lt.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R2, R3}, EMPTY},
|
||||
{"cmp.le.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R3, R2}, EMPTY},
|
||||
{"cmp.gt.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R3, R2}, EMPTY},
|
||||
{"cmp.ge.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R2, R3}, EMPTY},
|
||||
{"cmp.eq.and", A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}, EMPTY},
|
||||
{"cmp.ne.andcm", A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp.ne.and", A2, OpX2TbTaC (0xc, 0, 0, 1, 1), {P1, P2, R2, R3}, EMPTY},
|
||||
{"cmp.eq.andcm", A2, OpX2TbTaC (0xc, 0, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp4.lt", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P1, P2, R2, R3}, EMPTY},
|
||||
{"cmp4.le", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P2, P1, R3, R2}, EMPTY},
|
||||
{"cmp4.gt", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P1, P2, R3, R2}, EMPTY},
|
||||
{"cmp4.ge", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P2, P1, R2, R3}, EMPTY},
|
||||
{"cmp4.lt.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P1, P2, R2, R3}, EMPTY},
|
||||
{"cmp4.le.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P2, P1, R3, R2}, EMPTY},
|
||||
{"cmp4.gt.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P1, P2, R3, R2}, EMPTY},
|
||||
{"cmp4.ge.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P2, P1, R2, R3}, EMPTY},
|
||||
{"cmp4.eq.and", A2, OpX2TbTaC (0xc, 1, 0, 1, 0), {P1, P2, R2, R3}, EMPTY},
|
||||
{"cmp4.ne.andcm", A2, OpX2TbTaC (0xc, 1, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp4.ne.and", A2, OpX2TbTaC (0xc, 1, 0, 1, 1), {P1, P2, R2, R3}, EMPTY},
|
||||
{"cmp4.eq.andcm", A2, OpX2TbTaC (0xc, 1, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp.gt.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, GR0, R3}, EMPTY},
|
||||
{"cmp.lt.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp.le.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp.ge.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp.le.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, GR0, R3}, EMPTY},
|
||||
{"cmp.ge.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp.gt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp.lt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp.ge.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, GR0, R3}, EMPTY},
|
||||
{"cmp.le.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp.lt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp.gt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp.lt.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, GR0, R3}, EMPTY},
|
||||
{"cmp.gt.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp.ge.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp.le.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp4.gt.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, GR0, R3}, EMPTY},
|
||||
{"cmp4.lt.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp4.le.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp4.ge.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp4.le.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, GR0, R3}, EMPTY},
|
||||
{"cmp4.ge.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp4.gt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp4.lt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp4.ge.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, GR0, R3}, EMPTY},
|
||||
{"cmp4.le.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp4.lt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp4.gt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp4.lt.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, GR0, R3}, EMPTY},
|
||||
{"cmp4.gt.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp4.ge.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp4.le.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp.lt", A2, OpX2TaC (0xc, 2, 0, 0), {P1, P2, IMM8, R3}, EMPTY},
|
||||
{"cmp.le", A2, OpX2TaC (0xc, 2, 0, 0), {P1, P2, IMM8M1, R3}, EMPTY},
|
||||
{"cmp.gt", A2, OpX2TaC (0xc, 2, 0, 0), {P2, P1, IMM8M1, R3}, EMPTY},
|
||||
{"cmp.ge", A2, OpX2TaC (0xc, 2, 0, 0), {P2, P1, IMM8, R3}, EMPTY},
|
||||
{"cmp.lt.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P1, P2, IMM8, R3}, EMPTY},
|
||||
{"cmp.le.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P1, P2, IMM8M1, R3}, EMPTY},
|
||||
{"cmp.gt.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P2, P1, IMM8M1, R3}, EMPTY},
|
||||
{"cmp.ge.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P2, P1, IMM8, R3}, EMPTY},
|
||||
{"cmp.eq.and", A2, OpX2TaC (0xc, 2, 1, 0), {P1, P2, IMM8, R3}, EMPTY},
|
||||
{"cmp.ne.andcm", A2, OpX2TaC (0xc, 2, 1, 0), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp.ne.and", A2, OpX2TaC (0xc, 2, 1, 1), {P1, P2, IMM8, R3}, EMPTY},
|
||||
{"cmp.eq.andcm", A2, OpX2TaC (0xc, 2, 1, 1), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp4.lt", A2, OpX2TaC (0xc, 3, 0, 0), {P1, P2, IMM8, R3}, EMPTY},
|
||||
{"cmp4.le", A2, OpX2TaC (0xc, 3, 0, 0), {P1, P2, IMM8M1, R3}, EMPTY},
|
||||
{"cmp4.gt", A2, OpX2TaC (0xc, 3, 0, 0), {P2, P1, IMM8M1, R3}, EMPTY},
|
||||
{"cmp4.ge", A2, OpX2TaC (0xc, 3, 0, 0), {P2, P1, IMM8, R3}, EMPTY},
|
||||
{"cmp4.lt.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P1, P2, IMM8, R3}, EMPTY},
|
||||
{"cmp4.le.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P1, P2, IMM8M1, R3}, EMPTY},
|
||||
{"cmp4.gt.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P2, P1, IMM8M1, R3}, EMPTY},
|
||||
{"cmp4.ge.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P2, P1, IMM8, R3}, EMPTY},
|
||||
{"cmp4.eq.and", A2, OpX2TaC (0xc, 3, 1, 0), {P1, P2, IMM8, R3}, EMPTY},
|
||||
{"cmp4.ne.andcm", A2, OpX2TaC (0xc, 3, 1, 0), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp4.ne.and", A2, OpX2TaC (0xc, 3, 1, 1), {P1, P2, IMM8, R3}, EMPTY},
|
||||
{"cmp4.eq.andcm", A2, OpX2TaC (0xc, 3, 1, 1), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp.ltu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P1, P2, R2, R3}, EMPTY},
|
||||
{"cmp.leu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P2, P1, R3, R2}, EMPTY},
|
||||
{"cmp.gtu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P1, P2, R3, R2}, EMPTY},
|
||||
{"cmp.geu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P2, P1, R2, R3}, EMPTY},
|
||||
{"cmp.ltu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P1, P2, R2, R3}, EMPTY},
|
||||
{"cmp.leu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P2, P1, R3, R2}, EMPTY},
|
||||
{"cmp.gtu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P1, P2, R3, R2}, EMPTY},
|
||||
{"cmp.geu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P2, P1, R2, R3}, EMPTY},
|
||||
{"cmp.eq.or", A2, OpX2TbTaC (0xd, 0, 0, 1, 0), {P1, P2, R2, R3}, EMPTY},
|
||||
{"cmp.ne.orcm", A2, OpX2TbTaC (0xd, 0, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp.ne.or", A2, OpX2TbTaC (0xd, 0, 0, 1, 1), {P1, P2, R2, R3}, EMPTY},
|
||||
{"cmp.eq.orcm", A2, OpX2TbTaC (0xd, 0, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp4.ltu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P1, P2, R2, R3}, EMPTY},
|
||||
{"cmp4.leu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P2, P1, R3, R2}, EMPTY},
|
||||
{"cmp4.gtu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P1, P2, R3, R2}, EMPTY},
|
||||
{"cmp4.geu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P2, P1, R2, R3}, EMPTY},
|
||||
{"cmp4.ltu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P1, P2, R2, R3}, EMPTY},
|
||||
{"cmp4.leu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P2, P1, R3, R2}, EMPTY},
|
||||
{"cmp4.gtu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P1, P2, R3, R2}, EMPTY},
|
||||
{"cmp4.geu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P2, P1, R2, R3}, EMPTY},
|
||||
{"cmp4.eq.or", A2, OpX2TbTaC (0xd, 1, 0, 1, 0), {P1, P2, R2, R3}, EMPTY},
|
||||
{"cmp4.ne.orcm", A2, OpX2TbTaC (0xd, 1, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp4.ne.or", A2, OpX2TbTaC (0xd, 1, 0, 1, 1), {P1, P2, R2, R3}, EMPTY},
|
||||
{"cmp4.eq.orcm", A2, OpX2TbTaC (0xd, 1, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp.gt.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, GR0, R3}, EMPTY},
|
||||
{"cmp.lt.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp.le.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp.ge.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp.le.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, GR0, R3}, EMPTY},
|
||||
{"cmp.ge.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp.gt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp.lt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp.ge.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, GR0, R3}, EMPTY},
|
||||
{"cmp.le.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp.lt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp.gt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp.lt.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, GR0, R3}, EMPTY},
|
||||
{"cmp.gt.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp.ge.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp.le.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp4.gt.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, GR0, R3}, EMPTY},
|
||||
{"cmp4.lt.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp4.le.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp4.ge.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp4.le.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, GR0, R3}, EMPTY},
|
||||
{"cmp4.ge.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp4.gt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp4.lt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp4.ge.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, GR0, R3}, EMPTY},
|
||||
{"cmp4.le.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp4.lt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp4.gt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp4.lt.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, GR0, R3}, EMPTY},
|
||||
{"cmp4.gt.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp4.ge.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp4.le.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp.ltu", A2, OpX2TaC (0xd, 2, 0, 0), {P1, P2, IMM8, R3}, EMPTY},
|
||||
{"cmp.leu", A2, OpX2TaC (0xd, 2, 0, 0), {P1, P2, IMM8M1U8, R3}, EMPTY},
|
||||
{"cmp.gtu", A2, OpX2TaC (0xd, 2, 0, 0), {P2, P1, IMM8M1U8, R3}, EMPTY},
|
||||
{"cmp.geu", A2, OpX2TaC (0xd, 2, 0, 0), {P2, P1, IMM8, R3}, EMPTY},
|
||||
{"cmp.ltu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P1, P2, IMM8, R3}, EMPTY},
|
||||
{"cmp.leu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P1, P2, IMM8M1U8, R3}, EMPTY},
|
||||
{"cmp.gtu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P2, P1, IMM8M1U8, R3}, EMPTY},
|
||||
{"cmp.geu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P2, P1, IMM8, R3}, EMPTY},
|
||||
{"cmp.eq.or", A2, OpX2TaC (0xd, 2, 1, 0), {P1, P2, IMM8, R3}, EMPTY},
|
||||
{"cmp.ne.orcm", A2, OpX2TaC (0xd, 2, 1, 0), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp.ne.or", A2, OpX2TaC (0xd, 2, 1, 1), {P1, P2, IMM8, R3}, EMPTY},
|
||||
{"cmp.eq.orcm", A2, OpX2TaC (0xd, 2, 1, 1), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp4.ltu", A2, OpX2TaC (0xd, 3, 0, 0), {P1, P2, IMM8U4, R3}, EMPTY},
|
||||
{"cmp4.leu", A2, OpX2TaC (0xd, 3, 0, 0), {P1, P2, IMM8M1U4, R3}, EMPTY},
|
||||
{"cmp4.gtu", A2, OpX2TaC (0xd, 3, 0, 0), {P2, P1, IMM8M1U4, R3}, EMPTY},
|
||||
{"cmp4.geu", A2, OpX2TaC (0xd, 3, 0, 0), {P2, P1, IMM8U4, R3}, EMPTY},
|
||||
{"cmp4.ltu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P1, P2, IMM8U4, R3}, EMPTY},
|
||||
{"cmp4.leu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P1, P2, IMM8M1U4, R3}, EMPTY},
|
||||
{"cmp4.gtu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P2, P1, IMM8M1U4, R3}, EMPTY},
|
||||
{"cmp4.geu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P2, P1, IMM8U4, R3}, EMPTY},
|
||||
{"cmp4.eq.or", A2, OpX2TaC (0xd, 3, 1, 0), {P1, P2, IMM8, R3}, EMPTY},
|
||||
{"cmp4.ne.orcm", A2, OpX2TaC (0xd, 3, 1, 0), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp4.ne.or", A2, OpX2TaC (0xd, 3, 1, 1), {P1, P2, IMM8, R3}, EMPTY},
|
||||
{"cmp4.eq.orcm", A2, OpX2TaC (0xd, 3, 1, 1), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp.eq", A2, OpX2TbTaC (0xe, 0, 0, 0, 0), {P1, P2, R2, R3}, EMPTY},
|
||||
{"cmp.ne", A2, OpX2TbTaC (0xe, 0, 0, 0, 0), {P2, P1, R2, R3}, EMPTY},
|
||||
{"cmp.eq.unc", A2, OpX2TbTaC (0xe, 0, 0, 0, 1), {P1, P2, R2, R3}, EMPTY},
|
||||
{"cmp.ne.unc", A2, OpX2TbTaC (0xe, 0, 0, 0, 1), {P2, P1, R2, R3}, EMPTY},
|
||||
{"cmp.eq.or.andcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 0), {P1, P2, R2, R3}, EMPTY},
|
||||
{"cmp.ne.and.orcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 0), {P2, P1, R2, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp.ne.or.andcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 1), {P1, P2, R2, R3}, EMPTY},
|
||||
{"cmp.eq.and.orcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 1), {P2, P1, R2, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp4.eq", A2, OpX2TbTaC (0xe, 1, 0, 0, 0), {P1, P2, R2, R3}, EMPTY},
|
||||
{"cmp4.ne", A2, OpX2TbTaC (0xe, 1, 0, 0, 0), {P2, P1, R2, R3}, EMPTY},
|
||||
{"cmp4.eq.unc", A2, OpX2TbTaC (0xe, 1, 0, 0, 1), {P1, P2, R2, R3}, EMPTY},
|
||||
{"cmp4.ne.unc", A2, OpX2TbTaC (0xe, 1, 0, 0, 1), {P2, P1, R2, R3}, EMPTY},
|
||||
{"cmp4.eq.or.andcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 0), {P1, P2, R2, R3}, EMPTY},
|
||||
{"cmp4.ne.and.orcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 0), {P2, P1, R2, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp4.ne.or.andcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 1), {P1, P2, R2, R3}, EMPTY},
|
||||
{"cmp4.eq.and.orcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 1), {P2, P1, R2, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp.gt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P1, P2, GR0, R3}, EMPTY},
|
||||
{"cmp.lt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp.le.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P2, P1, GR0, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp.ge.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P2, P1, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp.le.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P1, P2, GR0, R3}, EMPTY},
|
||||
{"cmp.ge.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp.gt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P2, P1, GR0, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp.lt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P2, P1, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp.ge.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P1, P2, GR0, R3}, EMPTY},
|
||||
{"cmp.le.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp.lt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P2, P1, GR0, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp.gt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P2, P1, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp.lt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P1, P2, GR0, R3}, EMPTY},
|
||||
{"cmp.gt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp.ge.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P2, P1, GR0, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp.le.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P2, P1, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp4.gt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P1, P2, GR0, R3}, EMPTY},
|
||||
{"cmp4.lt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp4.le.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P2, P1, GR0, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp4.ge.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P2, P1, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp4.le.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P1, P2, GR0, R3}, EMPTY},
|
||||
{"cmp4.ge.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp4.gt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P2, P1, GR0, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp4.lt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P2, P1, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp4.ge.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P1, P2, GR0, R3}, EMPTY},
|
||||
{"cmp4.le.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp4.lt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P2, P1, GR0, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp4.gt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P2, P1, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp4.lt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P1, P2, GR0, R3}, EMPTY},
|
||||
{"cmp4.gt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp4.ge.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P2, P1, GR0, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp4.le.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P2, P1, R3, GR0}, PSEUDO, 0, NULL},
|
||||
{"cmp.eq", A2, OpX2TaC (0xe, 2, 0, 0), {P1, P2, IMM8, R3}, EMPTY},
|
||||
{"cmp.ne", A2, OpX2TaC (0xe, 2, 0, 0), {P2, P1, IMM8, R3}, EMPTY},
|
||||
{"cmp.eq.unc", A2, OpX2TaC (0xe, 2, 0, 1), {P1, P2, IMM8, R3}, EMPTY},
|
||||
{"cmp.ne.unc", A2, OpX2TaC (0xe, 2, 0, 1), {P2, P1, IMM8, R3}, EMPTY},
|
||||
{"cmp.eq.or.andcm", A2, OpX2TaC (0xe, 2, 1, 0), {P1, P2, IMM8, R3}, EMPTY},
|
||||
{"cmp.ne.and.orcm", A2, OpX2TaC (0xe, 2, 1, 0), {P2, P1, IMM8, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp.ne.or.andcm", A2, OpX2TaC (0xe, 2, 1, 1), {P1, P2, IMM8, R3}, EMPTY},
|
||||
{"cmp.eq.and.orcm", A2, OpX2TaC (0xe, 2, 1, 1), {P2, P1, IMM8, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp4.eq", A2, OpX2TaC (0xe, 3, 0, 0), {P1, P2, IMM8, R3}, EMPTY},
|
||||
{"cmp4.ne", A2, OpX2TaC (0xe, 3, 0, 0), {P2, P1, IMM8, R3}, EMPTY},
|
||||
{"cmp4.eq.unc", A2, OpX2TaC (0xe, 3, 0, 1), {P1, P2, IMM8, R3}, EMPTY},
|
||||
{"cmp4.ne.unc", A2, OpX2TaC (0xe, 3, 0, 1), {P2, P1, IMM8, R3}, EMPTY},
|
||||
{"cmp4.eq.or.andcm", A2, OpX2TaC (0xe, 3, 1, 0), {P1, P2, IMM8, R3}, EMPTY},
|
||||
{"cmp4.ne.and.orcm", A2, OpX2TaC (0xe, 3, 1, 0), {P2, P1, IMM8, R3}, PSEUDO, 0, NULL},
|
||||
{"cmp4.ne.or.andcm", A2, OpX2TaC (0xe, 3, 1, 1), {P1, P2, IMM8, R3}, EMPTY},
|
||||
{"cmp4.eq.and.orcm", A2, OpX2TaC (0xe, 3, 1, 1), {P2, P1, IMM8, R3}, PSEUDO, 0, NULL},
|
||||
|
||||
{NULL, 0, 0, 0, 0, {0}, 0, 0, NULL}
|
||||
};
|
||||
|
||||
#undef A
|
||||
#undef A2
|
||||
#undef bC
|
||||
#undef bImm14
|
||||
#undef bR3a
|
||||
#undef bR3b
|
||||
#undef bTa
|
||||
#undef bTb
|
||||
#undef bVe
|
||||
#undef bX
|
||||
#undef bX2
|
||||
#undef bX2a
|
||||
#undef bX2b
|
||||
#undef bX4
|
||||
#undef bZa
|
||||
#undef bZb
|
||||
#undef mC
|
||||
#undef mImm14
|
||||
#undef mR3a
|
||||
#undef mR3b
|
||||
#undef mTa
|
||||
#undef mTb
|
||||
#undef mVe
|
||||
#undef mX
|
||||
#undef mX2
|
||||
#undef mX2a
|
||||
#undef mX2b
|
||||
#undef mX4
|
||||
#undef mZa
|
||||
#undef mZb
|
||||
#undef OpR3a
|
||||
#undef OpR3b
|
||||
#undef OpX2aVe
|
||||
#undef OpX2aVeImm14
|
||||
#undef OpX2aVeX4
|
||||
#undef OpX2aVeX4X2b
|
||||
#undef OpX2TbTaC
|
||||
#undef OpX2TaC
|
||||
#undef OpX2aZaZbX4
|
||||
#undef OpX2aZaZbX4X2b
|
||||
#undef EMPTY
|
||||
@@ -1,512 +0,0 @@
|
||||
/* ia64-opc-b.c -- IA-64 `B' opcode table.
|
||||
Copyright 1998, 1999, 2000, 2002, 2005, 2006
|
||||
Free Software Foundation, Inc.
|
||||
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
|
||||
|
||||
This file is part of GDB, GAS, and the GNU binutils.
|
||||
|
||||
GDB, GAS, and the GNU binutils are free software; you can redistribute
|
||||
them and/or modify them under the terms of the GNU General Public
|
||||
License as published by the Free Software Foundation; either version
|
||||
2, or (at your option) any later version.
|
||||
|
||||
GDB, GAS, and the GNU binutils are distributed in the hope that they
|
||||
will be useful, but WITHOUT ANY WARRANTY; without even the implied
|
||||
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
|
||||
the GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this file; see the file COPYING. If not, write to the
|
||||
Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
|
||||
02110-1301, USA. */
|
||||
|
||||
#include "ia64-opc.h"
|
||||
|
||||
#define B0 IA64_TYPE_B, 0
|
||||
#define B IA64_TYPE_B, 1
|
||||
|
||||
/* instruction bit fields: */
|
||||
#define bBtype(x) (((ia64_insn) ((x) & 0x7)) << 6)
|
||||
#define bD(x) (((ia64_insn) ((x) & 0x1)) << 35)
|
||||
#define bIh(x) (((ia64_insn) ((x) & 0x1)) << 35)
|
||||
#define bPa(x) (((ia64_insn) ((x) & 0x1)) << 12)
|
||||
#define bPr(x) (((ia64_insn) ((x) & 0x3f)) << 0)
|
||||
#define bWha(x) (((ia64_insn) ((x) & 0x3)) << 33)
|
||||
#define bWhb(x) (((ia64_insn) ((x) & 0x3)) << 3)
|
||||
#define bWhc(x) (((ia64_insn) ((x) & 0x7)) << 32)
|
||||
#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27)
|
||||
|
||||
#define mBtype bBtype (-1)
|
||||
#define mD bD (-1)
|
||||
#define mIh bIh (-1)
|
||||
#define mPa bPa (-1)
|
||||
#define mPr bPr (-1)
|
||||
#define mWha bWha (-1)
|
||||
#define mWhb bWhb (-1)
|
||||
#define mWhc bWhc (-1)
|
||||
#define mX6 bX6 (-1)
|
||||
|
||||
#define OpX6(a,b) (bOp (a) | bX6 (b)), (mOp | mX6)
|
||||
#define OpPaWhaD(a,b,c,d) \
|
||||
(bOp (a) | bPa (b) | bWha (c) | bD (d)), (mOp | mPa | mWha | mD)
|
||||
#define OpPaWhcD(a,b,c,d) \
|
||||
(bOp (a) | bPa (b) | bWhc (c) | bD (d)), (mOp | mPa | mWhc | mD)
|
||||
#define OpBtypePaWhaD(a,b,c,d,e) \
|
||||
(bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e)), \
|
||||
(mOp | mBtype | mPa | mWha | mD)
|
||||
#define OpBtypePaWhaDPr(a,b,c,d,e,f) \
|
||||
(bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e) | bPr (f)), \
|
||||
(mOp | mBtype | mPa | mWha | mD | mPr)
|
||||
#define OpX6BtypePaWhaD(a,b,c,d,e,f) \
|
||||
(bOp (a) | bX6 (b) | bBtype (c) | bPa (d) | bWha (e) | bD (f)), \
|
||||
(mOp | mX6 | mBtype | mPa | mWha | mD)
|
||||
#define OpX6BtypePaWhaDPr(a,b,c,d,e,f,g) \
|
||||
(bOp (a) | bX6 (b) | bBtype (c) | bPa (d) | bWha (e) | bD (f) | bPr (g)), \
|
||||
(mOp | mX6 | mBtype | mPa | mWha | mD | mPr)
|
||||
#define OpIhWhb(a,b,c) \
|
||||
(bOp (a) | bIh (b) | bWhb (c)), \
|
||||
(mOp | mIh | mWhb)
|
||||
#define OpX6IhWhb(a,b,c,d) \
|
||||
(bOp (a) | bX6 (b) | bIh (c) | bWhb (d)), \
|
||||
(mOp | mX6 | mIh | mWhb)
|
||||
|
||||
/* Used to initialise unused fields in ia64_opcode struct,
|
||||
in order to stop gcc from complaining. */
|
||||
#define EMPTY 0,0,NULL
|
||||
|
||||
struct ia64_opcode ia64_opcodes_b[] =
|
||||
{
|
||||
/* B-type instruction encodings (sorted according to major opcode) */
|
||||
|
||||
#define BR(a,b) \
|
||||
B0, OpX6BtypePaWhaDPr (0, 0x20, 0, a, 0, b, 0), {B2}, PSEUDO, 0, NULL
|
||||
{"br.few", BR (0, 0)},
|
||||
{"br", BR (0, 0)},
|
||||
{"br.few.clr", BR (0, 1)},
|
||||
{"br.clr", BR (0, 1)},
|
||||
{"br.many", BR (1, 0)},
|
||||
{"br.many.clr", BR (1, 1)},
|
||||
#undef BR
|
||||
|
||||
#define BR(a,b,c,d,e) B0, OpX6BtypePaWhaD (0, a, b, c, d, e), {B2}, EMPTY
|
||||
#define BRP(a,b,c,d,e) B0, OpX6BtypePaWhaD (0, a, b, c, d, e), {B2}, PSEUDO, 0, NULL
|
||||
#define BRT(a,b,c,d,e,f) B0, OpX6BtypePaWhaD (0, a, b, c, d, e), {B2}, f, 0, NULL
|
||||
{"br.cond.sptk.few", BR (0x20, 0, 0, 0, 0)},
|
||||
{"br.cond.sptk", BRP (0x20, 0, 0, 0, 0)},
|
||||
{"br.cond.sptk.few.clr", BR (0x20, 0, 0, 0, 1)},
|
||||
{"br.cond.sptk.clr", BRP (0x20, 0, 0, 0, 1)},
|
||||
{"br.cond.spnt.few", BR (0x20, 0, 0, 1, 0)},
|
||||
{"br.cond.spnt", BRP (0x20, 0, 0, 1, 0)},
|
||||
{"br.cond.spnt.few.clr", BR (0x20, 0, 0, 1, 1)},
|
||||
{"br.cond.spnt.clr", BRP (0x20, 0, 0, 1, 1)},
|
||||
{"br.cond.dptk.few", BR (0x20, 0, 0, 2, 0)},
|
||||
{"br.cond.dptk", BRP (0x20, 0, 0, 2, 0)},
|
||||
{"br.cond.dptk.few.clr", BR (0x20, 0, 0, 2, 1)},
|
||||
{"br.cond.dptk.clr", BRP (0x20, 0, 0, 2, 1)},
|
||||
{"br.cond.dpnt.few", BR (0x20, 0, 0, 3, 0)},
|
||||
{"br.cond.dpnt", BRP (0x20, 0, 0, 3, 0)},
|
||||
{"br.cond.dpnt.few.clr", BR (0x20, 0, 0, 3, 1)},
|
||||
{"br.cond.dpnt.clr", BRP (0x20, 0, 0, 3, 1)},
|
||||
{"br.cond.sptk.many", BR (0x20, 0, 1, 0, 0)},
|
||||
{"br.cond.sptk.many.clr", BR (0x20, 0, 1, 0, 1)},
|
||||
{"br.cond.spnt.many", BR (0x20, 0, 1, 1, 0)},
|
||||
{"br.cond.spnt.many.clr", BR (0x20, 0, 1, 1, 1)},
|
||||
{"br.cond.dptk.many", BR (0x20, 0, 1, 2, 0)},
|
||||
{"br.cond.dptk.many.clr", BR (0x20, 0, 1, 2, 1)},
|
||||
{"br.cond.dpnt.many", BR (0x20, 0, 1, 3, 0)},
|
||||
{"br.cond.dpnt.many.clr", BR (0x20, 0, 1, 3, 1)},
|
||||
{"br.sptk.few", BR (0x20, 0, 0, 0, 0)},
|
||||
{"br.sptk", BRP (0x20, 0, 0, 0, 0)},
|
||||
{"br.sptk.few.clr", BR (0x20, 0, 0, 0, 1)},
|
||||
{"br.sptk.clr", BRP (0x20, 0, 0, 0, 1)},
|
||||
{"br.spnt.few", BR (0x20, 0, 0, 1, 0)},
|
||||
{"br.spnt", BRP (0x20, 0, 0, 1, 0)},
|
||||
{"br.spnt.few.clr", BR (0x20, 0, 0, 1, 1)},
|
||||
{"br.spnt.clr", BRP (0x20, 0, 0, 1, 1)},
|
||||
{"br.dptk.few", BR (0x20, 0, 0, 2, 0)},
|
||||
{"br.dptk", BRP (0x20, 0, 0, 2, 0)},
|
||||
{"br.dptk.few.clr", BR (0x20, 0, 0, 2, 1)},
|
||||
{"br.dptk.clr", BRP (0x20, 0, 0, 2, 1)},
|
||||
{"br.dpnt.few", BR (0x20, 0, 0, 3, 0)},
|
||||
{"br.dpnt", BRP (0x20, 0, 0, 3, 0)},
|
||||
{"br.dpnt.few.clr", BR (0x20, 0, 0, 3, 1)},
|
||||
{"br.dpnt.clr", BRP (0x20, 0, 0, 3, 1)},
|
||||
{"br.sptk.many", BR (0x20, 0, 1, 0, 0)},
|
||||
{"br.sptk.many.clr", BR (0x20, 0, 1, 0, 1)},
|
||||
{"br.spnt.many", BR (0x20, 0, 1, 1, 0)},
|
||||
{"br.spnt.many.clr", BR (0x20, 0, 1, 1, 1)},
|
||||
{"br.dptk.many", BR (0x20, 0, 1, 2, 0)},
|
||||
{"br.dptk.many.clr", BR (0x20, 0, 1, 2, 1)},
|
||||
{"br.dpnt.many", BR (0x20, 0, 1, 3, 0)},
|
||||
{"br.dpnt.many.clr", BR (0x20, 0, 1, 3, 1)},
|
||||
{"br.ia.sptk.few", BR (0x20, 1, 0, 0, 0)},
|
||||
{"br.ia.sptk", BRP (0x20, 1, 0, 0, 0)},
|
||||
{"br.ia.sptk.few.clr", BR (0x20, 1, 0, 0, 1)},
|
||||
{"br.ia.sptk.clr", BRP (0x20, 1, 0, 0, 1)},
|
||||
{"br.ia.spnt.few", BR (0x20, 1, 0, 1, 0)},
|
||||
{"br.ia.spnt", BRP (0x20, 1, 0, 1, 0)},
|
||||
{"br.ia.spnt.few.clr", BR (0x20, 1, 0, 1, 1)},
|
||||
{"br.ia.spnt.clr", BRP (0x20, 1, 0, 1, 1)},
|
||||
{"br.ia.dptk.few", BR (0x20, 1, 0, 2, 0)},
|
||||
{"br.ia.dptk", BRP (0x20, 1, 0, 2, 0)},
|
||||
{"br.ia.dptk.few.clr", BR (0x20, 1, 0, 2, 1)},
|
||||
{"br.ia.dptk.clr", BRP (0x20, 1, 0, 2, 1)},
|
||||
{"br.ia.dpnt.few", BR (0x20, 1, 0, 3, 0)},
|
||||
{"br.ia.dpnt", BRP (0x20, 1, 0, 3, 0)},
|
||||
{"br.ia.dpnt.few.clr", BR (0x20, 1, 0, 3, 1)},
|
||||
{"br.ia.dpnt.clr", BRP (0x20, 1, 0, 3, 1)},
|
||||
{"br.ia.sptk.many", BR (0x20, 1, 1, 0, 0)},
|
||||
{"br.ia.sptk.many.clr", BR (0x20, 1, 1, 0, 1)},
|
||||
{"br.ia.spnt.many", BR (0x20, 1, 1, 1, 0)},
|
||||
{"br.ia.spnt.many.clr", BR (0x20, 1, 1, 1, 1)},
|
||||
{"br.ia.dptk.many", BR (0x20, 1, 1, 2, 0)},
|
||||
{"br.ia.dptk.many.clr", BR (0x20, 1, 1, 2, 1)},
|
||||
{"br.ia.dpnt.many", BR (0x20, 1, 1, 3, 0)},
|
||||
{"br.ia.dpnt.many.clr", BR (0x20, 1, 1, 3, 1)},
|
||||
{"br.ret.sptk.few", BRT (0x21, 4, 0, 0, 0, MOD_RRBS)},
|
||||
{"br.ret.sptk", BRT (0x21, 4, 0, 0, 0, PSEUDO | MOD_RRBS)},
|
||||
{"br.ret.sptk.few.clr", BRT (0x21, 4, 0, 0, 1, MOD_RRBS)},
|
||||
{"br.ret.sptk.clr", BRT (0x21, 4, 0, 0, 1, PSEUDO | MOD_RRBS)},
|
||||
{"br.ret.spnt.few", BRT (0x21, 4, 0, 1, 0, MOD_RRBS)},
|
||||
{"br.ret.spnt", BRT (0x21, 4, 0, 1, 0, PSEUDO | MOD_RRBS)},
|
||||
{"br.ret.spnt.few.clr", BRT (0x21, 4, 0, 1, 1, MOD_RRBS)},
|
||||
{"br.ret.spnt.clr", BRT (0x21, 4, 0, 1, 1, PSEUDO | MOD_RRBS)},
|
||||
{"br.ret.dptk.few", BRT (0x21, 4, 0, 2, 0, MOD_RRBS)},
|
||||
{"br.ret.dptk", BRT (0x21, 4, 0, 2, 0, PSEUDO | MOD_RRBS)},
|
||||
{"br.ret.dptk.few.clr", BRT (0x21, 4, 0, 2, 1, MOD_RRBS)},
|
||||
{"br.ret.dptk.clr", BRT (0x21, 4, 0, 2, 1, PSEUDO | MOD_RRBS)},
|
||||
{"br.ret.dpnt.few", BRT (0x21, 4, 0, 3, 0, MOD_RRBS)},
|
||||
{"br.ret.dpnt", BRT (0x21, 4, 0, 3, 0, PSEUDO | MOD_RRBS)},
|
||||
{"br.ret.dpnt.few.clr", BRT (0x21, 4, 0, 3, 1, MOD_RRBS)},
|
||||
{"br.ret.dpnt.clr", BRT (0x21, 4, 0, 3, 1, PSEUDO | MOD_RRBS)},
|
||||
{"br.ret.sptk.many", BRT (0x21, 4, 1, 0, 0, MOD_RRBS)},
|
||||
{"br.ret.sptk.many.clr", BRT (0x21, 4, 1, 0, 1, MOD_RRBS)},
|
||||
{"br.ret.spnt.many", BRT (0x21, 4, 1, 1, 0, MOD_RRBS)},
|
||||
{"br.ret.spnt.many.clr", BRT (0x21, 4, 1, 1, 1, MOD_RRBS)},
|
||||
{"br.ret.dptk.many", BRT (0x21, 4, 1, 2, 0, MOD_RRBS)},
|
||||
{"br.ret.dptk.many.clr", BRT (0x21, 4, 1, 2, 1, MOD_RRBS)},
|
||||
{"br.ret.dpnt.many", BRT (0x21, 4, 1, 3, 0, MOD_RRBS)},
|
||||
{"br.ret.dpnt.many.clr", BRT (0x21, 4, 1, 3, 1, MOD_RRBS)},
|
||||
#undef BR
|
||||
#undef BRP
|
||||
#undef BRT
|
||||
|
||||
{"cover", B0, OpX6 (0, 0x02), {0, }, NO_PRED | LAST | MOD_RRBS, 0, NULL},
|
||||
{"clrrrb", B0, OpX6 (0, 0x04), {0, }, NO_PRED | LAST | MOD_RRBS, 0, NULL},
|
||||
{"clrrrb.pr", B0, OpX6 (0, 0x05), {0, }, NO_PRED | LAST | MOD_RRBS, 0, NULL},
|
||||
{"rfi", B0, OpX6 (0, 0x08), {0, }, NO_PRED | LAST | PRIV | MOD_RRBS, 0, NULL},
|
||||
{"bsw.0", B0, OpX6 (0, 0x0c), {0, }, NO_PRED | LAST | PRIV, 0, NULL},
|
||||
{"bsw.1", B0, OpX6 (0, 0x0d), {0, }, NO_PRED | LAST | PRIV, 0, NULL},
|
||||
{"epc", B0, OpX6 (0, 0x10), {0, }, NO_PRED, 0, NULL},
|
||||
{"vmsw.0", B0, OpX6 (0, 0x18), {0, }, NO_PRED | PRIV, 0, NULL},
|
||||
{"vmsw.1", B0, OpX6 (0, 0x19), {0, }, NO_PRED | PRIV, 0, NULL},
|
||||
|
||||
{"break.b", B0, OpX6 (0, 0x00), {IMMU21}, EMPTY},
|
||||
|
||||
{"br.call.sptk.few", B, OpPaWhcD (1, 0, 1, 0), {B1, B2}, EMPTY},
|
||||
{"br.call.sptk", B, OpPaWhcD (1, 0, 1, 0), {B1, B2}, PSEUDO, 0, NULL},
|
||||
{"br.call.sptk.few.clr", B, OpPaWhcD (1, 0, 1, 1), {B1, B2}, EMPTY},
|
||||
{"br.call.sptk.clr", B, OpPaWhcD (1, 0, 1, 1), {B1, B2}, PSEUDO, 0, NULL},
|
||||
{"br.call.spnt.few", B, OpPaWhcD (1, 0, 3, 0), {B1, B2}, EMPTY},
|
||||
{"br.call.spnt", B, OpPaWhcD (1, 0, 3, 0), {B1, B2}, PSEUDO, 0, NULL},
|
||||
{"br.call.spnt.few.clr", B, OpPaWhcD (1, 0, 3, 1), {B1, B2}, EMPTY},
|
||||
{"br.call.spnt.clr", B, OpPaWhcD (1, 0, 3, 1), {B1, B2}, PSEUDO, 0, NULL},
|
||||
{"br.call.dptk.few", B, OpPaWhcD (1, 0, 5, 0), {B1, B2}, EMPTY},
|
||||
{"br.call.dptk", B, OpPaWhcD (1, 0, 5, 0), {B1, B2}, PSEUDO, 0, NULL},
|
||||
{"br.call.dptk.few.clr", B, OpPaWhcD (1, 0, 5, 1), {B1, B2}, EMPTY},
|
||||
{"br.call.dptk.clr", B, OpPaWhcD (1, 0, 5, 1), {B1, B2}, PSEUDO, 0, NULL},
|
||||
{"br.call.dpnt.few", B, OpPaWhcD (1, 0, 7, 0), {B1, B2}, EMPTY},
|
||||
{"br.call.dpnt", B, OpPaWhcD (1, 0, 7, 0), {B1, B2}, PSEUDO, 0, NULL},
|
||||
{"br.call.dpnt.few.clr", B, OpPaWhcD (1, 0, 7, 1), {B1, B2}, EMPTY},
|
||||
{"br.call.dpnt.clr", B, OpPaWhcD (1, 0, 7, 1), {B1, B2}, PSEUDO, 0, NULL},
|
||||
{"br.call.sptk.many", B, OpPaWhcD (1, 1, 1, 0), {B1, B2}, EMPTY},
|
||||
{"br.call.sptk.many.clr", B, OpPaWhcD (1, 1, 1, 1), {B1, B2}, EMPTY},
|
||||
{"br.call.spnt.many", B, OpPaWhcD (1, 1, 3, 0), {B1, B2}, EMPTY},
|
||||
{"br.call.spnt.many.clr", B, OpPaWhcD (1, 1, 3, 1), {B1, B2}, EMPTY},
|
||||
{"br.call.dptk.many", B, OpPaWhcD (1, 1, 5, 0), {B1, B2}, EMPTY},
|
||||
{"br.call.dptk.many.clr", B, OpPaWhcD (1, 1, 5, 1), {B1, B2}, EMPTY},
|
||||
{"br.call.dpnt.many", B, OpPaWhcD (1, 1, 7, 0), {B1, B2}, EMPTY},
|
||||
{"br.call.dpnt.many.clr", B, OpPaWhcD (1, 1, 7, 1), {B1, B2}, EMPTY},
|
||||
|
||||
#define BRP(a,b,c) \
|
||||
B0, OpX6IhWhb (2, a, b, c), {B2, TAG13}, NO_PRED, 0, NULL
|
||||
{"brp.sptk", BRP (0x10, 0, 0)},
|
||||
{"brp.dptk", BRP (0x10, 0, 2)},
|
||||
{"brp.sptk.imp", BRP (0x10, 1, 0)},
|
||||
{"brp.dptk.imp", BRP (0x10, 1, 2)},
|
||||
{"brp.ret.sptk", BRP (0x11, 0, 0)},
|
||||
{"brp.ret.dptk", BRP (0x11, 0, 2)},
|
||||
{"brp.ret.sptk.imp", BRP (0x11, 1, 0)},
|
||||
{"brp.ret.dptk.imp", BRP (0x11, 1, 2)},
|
||||
#undef BRP
|
||||
|
||||
{"nop.b", B0, OpX6 (2, 0x00), {IMMU21}, EMPTY},
|
||||
{"hint.b", B0, OpX6 (2, 0x01), {IMMU21}, EMPTY},
|
||||
|
||||
#define BR(a,b) \
|
||||
B0, OpBtypePaWhaDPr (4, 0, a, 0, b, 0), {TGT25c}, PSEUDO, 0, NULL
|
||||
{"br.few", BR (0, 0)},
|
||||
{"br", BR (0, 0)},
|
||||
{"br.few.clr", BR (0, 1)},
|
||||
{"br.clr", BR (0, 1)},
|
||||
{"br.many", BR (1, 0)},
|
||||
{"br.many.clr", BR (1, 1)},
|
||||
#undef BR
|
||||
|
||||
#define BR(a,b,c) \
|
||||
B0, OpBtypePaWhaD (4, 0, a, b, c), {TGT25c}, EMPTY
|
||||
#define BRP(a,b,c) \
|
||||
B0, OpBtypePaWhaD (4, 0, a, b, c), {TGT25c}, PSEUDO, 0, NULL
|
||||
{"br.cond.sptk.few", BR (0, 0, 0)},
|
||||
{"br.cond.sptk", BRP (0, 0, 0)},
|
||||
{"br.cond.sptk.few.clr", BR (0, 0, 1)},
|
||||
{"br.cond.sptk.clr", BRP (0, 0, 1)},
|
||||
{"br.cond.spnt.few", BR (0, 1, 0)},
|
||||
{"br.cond.spnt", BRP (0, 1, 0)},
|
||||
{"br.cond.spnt.few.clr", BR (0, 1, 1)},
|
||||
{"br.cond.spnt.clr", BRP (0, 1, 1)},
|
||||
{"br.cond.dptk.few", BR (0, 2, 0)},
|
||||
{"br.cond.dptk", BRP (0, 2, 0)},
|
||||
{"br.cond.dptk.few.clr", BR (0, 2, 1)},
|
||||
{"br.cond.dptk.clr", BRP (0, 2, 1)},
|
||||
{"br.cond.dpnt.few", BR (0, 3, 0)},
|
||||
{"br.cond.dpnt", BRP (0, 3, 0)},
|
||||
{"br.cond.dpnt.few.clr", BR (0, 3, 1)},
|
||||
{"br.cond.dpnt.clr", BRP (0, 3, 1)},
|
||||
{"br.cond.sptk.many", BR (1, 0, 0)},
|
||||
{"br.cond.sptk.many.clr", BR (1, 0, 1)},
|
||||
{"br.cond.spnt.many", BR (1, 1, 0)},
|
||||
{"br.cond.spnt.many.clr", BR (1, 1, 1)},
|
||||
{"br.cond.dptk.many", BR (1, 2, 0)},
|
||||
{"br.cond.dptk.many.clr", BR (1, 2, 1)},
|
||||
{"br.cond.dpnt.many", BR (1, 3, 0)},
|
||||
{"br.cond.dpnt.many.clr", BR (1, 3, 1)},
|
||||
{"br.sptk.few", BR (0, 0, 0)},
|
||||
{"br.sptk", BRP (0, 0, 0)},
|
||||
{"br.sptk.few.clr", BR (0, 0, 1)},
|
||||
{"br.sptk.clr", BRP (0, 0, 1)},
|
||||
{"br.spnt.few", BR (0, 1, 0)},
|
||||
{"br.spnt", BRP (0, 1, 0)},
|
||||
{"br.spnt.few.clr", BR (0, 1, 1)},
|
||||
{"br.spnt.clr", BRP (0, 1, 1)},
|
||||
{"br.dptk.few", BR (0, 2, 0)},
|
||||
{"br.dptk", BRP (0, 2, 0)},
|
||||
{"br.dptk.few.clr", BR (0, 2, 1)},
|
||||
{"br.dptk.clr", BRP (0, 2, 1)},
|
||||
{"br.dpnt.few", BR (0, 3, 0)},
|
||||
{"br.dpnt", BRP (0, 3, 0)},
|
||||
{"br.dpnt.few.clr", BR (0, 3, 1)},
|
||||
{"br.dpnt.clr", BRP (0, 3, 1)},
|
||||
{"br.sptk.many", BR (1, 0, 0)},
|
||||
{"br.sptk.many.clr", BR (1, 0, 1)},
|
||||
{"br.spnt.many", BR (1, 1, 0)},
|
||||
{"br.spnt.many.clr", BR (1, 1, 1)},
|
||||
{"br.dptk.many", BR (1, 2, 0)},
|
||||
{"br.dptk.many.clr", BR (1, 2, 1)},
|
||||
{"br.dpnt.many", BR (1, 3, 0)},
|
||||
{"br.dpnt.many.clr", BR (1, 3, 1)},
|
||||
#undef BR
|
||||
#undef BRP
|
||||
|
||||
#define BR(a,b,c,d, e) \
|
||||
B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2 | e, 0, NULL
|
||||
{"br.wexit.sptk.few", BR (2, 0, 0, 0, MOD_RRBS)},
|
||||
{"br.wexit.sptk", BR (2, 0, 0, 0, PSEUDO | MOD_RRBS)},
|
||||
{"br.wexit.sptk.few.clr", BR (2, 0, 0, 1, MOD_RRBS)},
|
||||
{"br.wexit.sptk.clr", BR (2, 0, 0, 1, PSEUDO | MOD_RRBS)},
|
||||
{"br.wexit.spnt.few", BR (2, 0, 1, 0, MOD_RRBS)},
|
||||
{"br.wexit.spnt", BR (2, 0, 1, 0, PSEUDO | MOD_RRBS)},
|
||||
{"br.wexit.spnt.few.clr", BR (2, 0, 1, 1, MOD_RRBS)},
|
||||
{"br.wexit.spnt.clr", BR (2, 0, 1, 1, PSEUDO | MOD_RRBS)},
|
||||
{"br.wexit.dptk.few", BR (2, 0, 2, 0, MOD_RRBS)},
|
||||
{"br.wexit.dptk", BR (2, 0, 2, 0, PSEUDO | MOD_RRBS)},
|
||||
{"br.wexit.dptk.few.clr", BR (2, 0, 2, 1, MOD_RRBS)},
|
||||
{"br.wexit.dptk.clr", BR (2, 0, 2, 1, PSEUDO | MOD_RRBS)},
|
||||
{"br.wexit.dpnt.few", BR (2, 0, 3, 0, MOD_RRBS)},
|
||||
{"br.wexit.dpnt", BR (2, 0, 3, 0, PSEUDO | MOD_RRBS)},
|
||||
{"br.wexit.dpnt.few.clr", BR (2, 0, 3, 1, MOD_RRBS)},
|
||||
{"br.wexit.dpnt.clr", BR (2, 0, 3, 1, PSEUDO | MOD_RRBS)},
|
||||
{"br.wexit.sptk.many", BR (2, 1, 0, 0, MOD_RRBS)},
|
||||
{"br.wexit.sptk.many.clr", BR (2, 1, 0, 1, MOD_RRBS)},
|
||||
{"br.wexit.spnt.many", BR (2, 1, 1, 0, MOD_RRBS)},
|
||||
{"br.wexit.spnt.many.clr", BR (2, 1, 1, 1, MOD_RRBS)},
|
||||
{"br.wexit.dptk.many", BR (2, 1, 2, 0, MOD_RRBS)},
|
||||
{"br.wexit.dptk.many.clr", BR (2, 1, 2, 1, MOD_RRBS)},
|
||||
{"br.wexit.dpnt.many", BR (2, 1, 3, 0, MOD_RRBS)},
|
||||
{"br.wexit.dpnt.many.clr", BR (2, 1, 3, 1, MOD_RRBS)},
|
||||
{"br.wtop.sptk.few", BR (3, 0, 0, 0, MOD_RRBS)},
|
||||
{"br.wtop.sptk", BR (3, 0, 0, 0, PSEUDO | MOD_RRBS)},
|
||||
{"br.wtop.sptk.few.clr", BR (3, 0, 0, 1, MOD_RRBS)},
|
||||
{"br.wtop.sptk.clr", BR (3, 0, 0, 1, PSEUDO | MOD_RRBS)},
|
||||
{"br.wtop.spnt.few", BR (3, 0, 1, 0, MOD_RRBS)},
|
||||
{"br.wtop.spnt", BR (3, 0, 1, 0, PSEUDO | MOD_RRBS)},
|
||||
{"br.wtop.spnt.few.clr", BR (3, 0, 1, 1, MOD_RRBS)},
|
||||
{"br.wtop.spnt.clr", BR (3, 0, 1, 1, PSEUDO | MOD_RRBS)},
|
||||
{"br.wtop.dptk.few", BR (3, 0, 2, 0, MOD_RRBS)},
|
||||
{"br.wtop.dptk", BR (3, 0, 2, 0, PSEUDO | MOD_RRBS)},
|
||||
{"br.wtop.dptk.few.clr", BR (3, 0, 2, 1, MOD_RRBS)},
|
||||
{"br.wtop.dptk.clr", BR (3, 0, 2, 1, PSEUDO | MOD_RRBS)},
|
||||
{"br.wtop.dpnt.few", BR (3, 0, 3, 0, MOD_RRBS)},
|
||||
{"br.wtop.dpnt", BR (3, 0, 3, 0, PSEUDO | MOD_RRBS)},
|
||||
{"br.wtop.dpnt.few.clr", BR (3, 0, 3, 1, MOD_RRBS)},
|
||||
{"br.wtop.dpnt.clr", BR (3, 0, 3, 1, PSEUDO | MOD_RRBS)},
|
||||
{"br.wtop.sptk.many", BR (3, 1, 0, 0, MOD_RRBS)},
|
||||
{"br.wtop.sptk.many.clr", BR (3, 1, 0, 1, MOD_RRBS)},
|
||||
{"br.wtop.spnt.many", BR (3, 1, 1, 0, MOD_RRBS)},
|
||||
{"br.wtop.spnt.many.clr", BR (3, 1, 1, 1, MOD_RRBS)},
|
||||
{"br.wtop.dptk.many", BR (3, 1, 2, 0, MOD_RRBS)},
|
||||
{"br.wtop.dptk.many.clr", BR (3, 1, 2, 1, MOD_RRBS)},
|
||||
{"br.wtop.dpnt.many", BR (3, 1, 3, 0, MOD_RRBS)},
|
||||
{"br.wtop.dpnt.many.clr", BR (3, 1, 3, 1, MOD_RRBS)},
|
||||
|
||||
#undef BR
|
||||
#define BR(a,b,c,d) \
|
||||
B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2 | NO_PRED, 0, NULL
|
||||
#define BRT(a,b,c,d,e) \
|
||||
B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2 | NO_PRED | e, 0, NULL
|
||||
{"br.cloop.sptk.few", BR (5, 0, 0, 0)},
|
||||
{"br.cloop.sptk", BRT (5, 0, 0, 0, PSEUDO)},
|
||||
{"br.cloop.sptk.few.clr", BR (5, 0, 0, 1)},
|
||||
{"br.cloop.sptk.clr", BRT (5, 0, 0, 1, PSEUDO)},
|
||||
{"br.cloop.spnt.few", BR (5, 0, 1, 0)},
|
||||
{"br.cloop.spnt", BRT (5, 0, 1, 0, PSEUDO)},
|
||||
{"br.cloop.spnt.few.clr", BR (5, 0, 1, 1)},
|
||||
{"br.cloop.spnt.clr", BRT (5, 0, 1, 1, PSEUDO)},
|
||||
{"br.cloop.dptk.few", BR (5, 0, 2, 0)},
|
||||
{"br.cloop.dptk", BRT (5, 0, 2, 0, PSEUDO)},
|
||||
{"br.cloop.dptk.few.clr", BR (5, 0, 2, 1)},
|
||||
{"br.cloop.dptk.clr", BRT (5, 0, 2, 1, PSEUDO)},
|
||||
{"br.cloop.dpnt.few", BR (5, 0, 3, 0)},
|
||||
{"br.cloop.dpnt", BRT (5, 0, 3, 0, PSEUDO)},
|
||||
{"br.cloop.dpnt.few.clr", BR (5, 0, 3, 1)},
|
||||
{"br.cloop.dpnt.clr", BRT (5, 0, 3, 1, PSEUDO)},
|
||||
{"br.cloop.sptk.many", BR (5, 1, 0, 0)},
|
||||
{"br.cloop.sptk.many.clr", BR (5, 1, 0, 1)},
|
||||
{"br.cloop.spnt.many", BR (5, 1, 1, 0)},
|
||||
{"br.cloop.spnt.many.clr", BR (5, 1, 1, 1)},
|
||||
{"br.cloop.dptk.many", BR (5, 1, 2, 0)},
|
||||
{"br.cloop.dptk.many.clr", BR (5, 1, 2, 1)},
|
||||
{"br.cloop.dpnt.many", BR (5, 1, 3, 0)},
|
||||
{"br.cloop.dpnt.many.clr", BR (5, 1, 3, 1)},
|
||||
{"br.cexit.sptk.few", BRT (6, 0, 0, 0, MOD_RRBS)},
|
||||
{"br.cexit.sptk", BRT (6, 0, 0, 0, PSEUDO | MOD_RRBS)},
|
||||
{"br.cexit.sptk.few.clr", BRT (6, 0, 0, 1, MOD_RRBS)},
|
||||
{"br.cexit.sptk.clr", BRT (6, 0, 0, 1, PSEUDO | MOD_RRBS)},
|
||||
{"br.cexit.spnt.few", BRT (6, 0, 1, 0, MOD_RRBS)},
|
||||
{"br.cexit.spnt", BRT (6, 0, 1, 0, PSEUDO | MOD_RRBS)},
|
||||
{"br.cexit.spnt.few.clr", BRT (6, 0, 1, 1, MOD_RRBS)},
|
||||
{"br.cexit.spnt.clr", BRT (6, 0, 1, 1, PSEUDO | MOD_RRBS)},
|
||||
{"br.cexit.dptk.few", BRT (6, 0, 2, 0, MOD_RRBS)},
|
||||
{"br.cexit.dptk", BRT (6, 0, 2, 0, PSEUDO | MOD_RRBS)},
|
||||
{"br.cexit.dptk.few.clr", BRT (6, 0, 2, 1, MOD_RRBS)},
|
||||
{"br.cexit.dptk.clr", BRT (6, 0, 2, 1, PSEUDO | MOD_RRBS)},
|
||||
{"br.cexit.dpnt.few", BRT (6, 0, 3, 0, MOD_RRBS)},
|
||||
{"br.cexit.dpnt", BRT (6, 0, 3, 0, PSEUDO | MOD_RRBS)},
|
||||
{"br.cexit.dpnt.few.clr", BRT (6, 0, 3, 1, MOD_RRBS)},
|
||||
{"br.cexit.dpnt.clr", BRT (6, 0, 3, 1, PSEUDO | MOD_RRBS)},
|
||||
{"br.cexit.sptk.many", BRT (6, 1, 0, 0, MOD_RRBS)},
|
||||
{"br.cexit.sptk.many.clr", BRT (6, 1, 0, 1, MOD_RRBS)},
|
||||
{"br.cexit.spnt.many", BRT (6, 1, 1, 0, MOD_RRBS)},
|
||||
{"br.cexit.spnt.many.clr", BRT (6, 1, 1, 1, MOD_RRBS)},
|
||||
{"br.cexit.dptk.many", BRT (6, 1, 2, 0, MOD_RRBS)},
|
||||
{"br.cexit.dptk.many.clr", BRT (6, 1, 2, 1, MOD_RRBS)},
|
||||
{"br.cexit.dpnt.many", BRT (6, 1, 3, 0, MOD_RRBS)},
|
||||
{"br.cexit.dpnt.many.clr", BRT (6, 1, 3, 1, MOD_RRBS)},
|
||||
{"br.ctop.sptk.few", BRT (7, 0, 0, 0, MOD_RRBS)},
|
||||
{"br.ctop.sptk", BRT (7, 0, 0, 0, PSEUDO | MOD_RRBS)},
|
||||
{"br.ctop.sptk.few.clr", BRT (7, 0, 0, 1, MOD_RRBS)},
|
||||
{"br.ctop.sptk.clr", BRT (7, 0, 0, 1, PSEUDO | MOD_RRBS)},
|
||||
{"br.ctop.spnt.few", BRT (7, 0, 1, 0, MOD_RRBS)},
|
||||
{"br.ctop.spnt", BRT (7, 0, 1, 0, PSEUDO | MOD_RRBS)},
|
||||
{"br.ctop.spnt.few.clr", BRT (7, 0, 1, 1, MOD_RRBS)},
|
||||
{"br.ctop.spnt.clr", BRT (7, 0, 1, 1, PSEUDO | MOD_RRBS)},
|
||||
{"br.ctop.dptk.few", BRT (7, 0, 2, 0, MOD_RRBS)},
|
||||
{"br.ctop.dptk", BRT (7, 0, 2, 0, PSEUDO | MOD_RRBS)},
|
||||
{"br.ctop.dptk.few.clr", BRT (7, 0, 2, 1, MOD_RRBS)},
|
||||
{"br.ctop.dptk.clr", BRT (7, 0, 2, 1, PSEUDO | MOD_RRBS)},
|
||||
{"br.ctop.dpnt.few", BRT (7, 0, 3, 0, MOD_RRBS)},
|
||||
{"br.ctop.dpnt", BRT (7, 0, 3, 0, PSEUDO | MOD_RRBS)},
|
||||
{"br.ctop.dpnt.few.clr", BRT (7, 0, 3, 1, MOD_RRBS)},
|
||||
{"br.ctop.dpnt.clr", BRT (7, 0, 3, 1, PSEUDO | MOD_RRBS)},
|
||||
{"br.ctop.sptk.many", BRT (7, 1, 0, 0, MOD_RRBS)},
|
||||
{"br.ctop.sptk.many.clr", BRT (7, 1, 0, 1, MOD_RRBS)},
|
||||
{"br.ctop.spnt.many", BRT (7, 1, 1, 0, MOD_RRBS)},
|
||||
{"br.ctop.spnt.many.clr", BRT (7, 1, 1, 1, MOD_RRBS)},
|
||||
{"br.ctop.dptk.many", BRT (7, 1, 2, 0, MOD_RRBS)},
|
||||
{"br.ctop.dptk.many.clr", BRT (7, 1, 2, 1, MOD_RRBS)},
|
||||
{"br.ctop.dpnt.many", BRT (7, 1, 3, 0, MOD_RRBS)},
|
||||
{"br.ctop.dpnt.many.clr", BRT (7, 1, 3, 1, MOD_RRBS)},
|
||||
#undef BR
|
||||
#undef BRT
|
||||
|
||||
{"br.call.sptk.few", B, OpPaWhaD (5, 0, 0, 0), {B1, TGT25c}, EMPTY},
|
||||
{"br.call.sptk", B, OpPaWhaD (5, 0, 0, 0), {B1, TGT25c}, PSEUDO, 0, NULL},
|
||||
{"br.call.sptk.few.clr", B, OpPaWhaD (5, 0, 0, 1), {B1, TGT25c}, EMPTY},
|
||||
{"br.call.sptk.clr", B, OpPaWhaD (5, 0, 0, 1), {B1, TGT25c}, PSEUDO, 0, NULL},
|
||||
{"br.call.spnt.few", B, OpPaWhaD (5, 0, 1, 0), {B1, TGT25c}, EMPTY},
|
||||
{"br.call.spnt", B, OpPaWhaD (5, 0, 1, 0), {B1, TGT25c}, PSEUDO, 0, NULL},
|
||||
{"br.call.spnt.few.clr", B, OpPaWhaD (5, 0, 1, 1), {B1, TGT25c}, EMPTY},
|
||||
{"br.call.spnt.clr", B, OpPaWhaD (5, 0, 1, 1), {B1, TGT25c}, PSEUDO, 0, NULL},
|
||||
{"br.call.dptk.few", B, OpPaWhaD (5, 0, 2, 0), {B1, TGT25c}, EMPTY},
|
||||
{"br.call.dptk", B, OpPaWhaD (5, 0, 2, 0), {B1, TGT25c}, PSEUDO, 0, NULL},
|
||||
{"br.call.dptk.few.clr", B, OpPaWhaD (5, 0, 2, 1), {B1, TGT25c}, EMPTY},
|
||||
{"br.call.dptk.clr", B, OpPaWhaD (5, 0, 2, 1), {B1, TGT25c}, PSEUDO, 0, NULL},
|
||||
{"br.call.dpnt.few", B, OpPaWhaD (5, 0, 3, 0), {B1, TGT25c}, EMPTY},
|
||||
{"br.call.dpnt", B, OpPaWhaD (5, 0, 3, 0), {B1, TGT25c}, PSEUDO, 0, NULL},
|
||||
{"br.call.dpnt.few.clr", B, OpPaWhaD (5, 0, 3, 1), {B1, TGT25c}, EMPTY},
|
||||
{"br.call.dpnt.clr", B, OpPaWhaD (5, 0, 3, 1), {B1, TGT25c}, PSEUDO, 0, NULL},
|
||||
{"br.call.sptk.many", B, OpPaWhaD (5, 1, 0, 0), {B1, TGT25c}, EMPTY},
|
||||
{"br.call.sptk.many.clr", B, OpPaWhaD (5, 1, 0, 1), {B1, TGT25c}, EMPTY},
|
||||
{"br.call.spnt.many", B, OpPaWhaD (5, 1, 1, 0), {B1, TGT25c}, EMPTY},
|
||||
{"br.call.spnt.many.clr", B, OpPaWhaD (5, 1, 1, 1), {B1, TGT25c}, EMPTY},
|
||||
{"br.call.dptk.many", B, OpPaWhaD (5, 1, 2, 0), {B1, TGT25c}, EMPTY},
|
||||
{"br.call.dptk.many.clr", B, OpPaWhaD (5, 1, 2, 1), {B1, TGT25c}, EMPTY},
|
||||
{"br.call.dpnt.many", B, OpPaWhaD (5, 1, 3, 0), {B1, TGT25c}, EMPTY},
|
||||
{"br.call.dpnt.many.clr", B, OpPaWhaD (5, 1, 3, 1), {B1, TGT25c}, EMPTY},
|
||||
|
||||
/* Branch predict. */
|
||||
#define BRP(a,b) \
|
||||
B0, OpIhWhb (7, a, b), {TGT25c, TAG13}, NO_PRED, 0, NULL
|
||||
{"brp.sptk", BRP (0, 0)},
|
||||
{"brp.loop", BRP (0, 1)},
|
||||
{"brp.dptk", BRP (0, 2)},
|
||||
{"brp.exit", BRP (0, 3)},
|
||||
{"brp.sptk.imp", BRP (1, 0)},
|
||||
{"brp.loop.imp", BRP (1, 1)},
|
||||
{"brp.dptk.imp", BRP (1, 2)},
|
||||
{"brp.exit.imp", BRP (1, 3)},
|
||||
#undef BRP
|
||||
|
||||
{NULL, 0, 0, 0, 0, {0}, 0, 0, NULL}
|
||||
};
|
||||
|
||||
#undef B0
|
||||
#undef B
|
||||
#undef bBtype
|
||||
#undef bD
|
||||
#undef bIh
|
||||
#undef bPa
|
||||
#undef bPr
|
||||
#undef bWha
|
||||
#undef bWhb
|
||||
#undef bWhc
|
||||
#undef bX6
|
||||
#undef mBtype
|
||||
#undef mD
|
||||
#undef mIh
|
||||
#undef mPa
|
||||
#undef mPr
|
||||
#undef mWha
|
||||
#undef mWhb
|
||||
#undef mWhc
|
||||
#undef mX6
|
||||
#undef OpX6
|
||||
#undef OpPaWhaD
|
||||
#undef OpPaWhcD
|
||||
#undef OpBtypePaWhaD
|
||||
#undef OpBtypePaWhaDPr
|
||||
#undef OpX6BtypePaWhaD
|
||||
#undef OpX6BtypePaWhaDPr
|
||||
#undef OpIhWhb
|
||||
#undef OpX6IhWhb
|
||||
#undef EMPTY
|
||||
@@ -1,34 +0,0 @@
|
||||
/* ia64-opc-d.c -- IA-64 `D' opcode table.
|
||||
Copyright 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
|
||||
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
|
||||
|
||||
This file is part of GDB, GAS, and the GNU binutils.
|
||||
|
||||
GDB, GAS, and the GNU binutils are free software; you can redistribute
|
||||
them and/or modify them under the terms of the GNU General Public
|
||||
License as published by the Free Software Foundation; either version
|
||||
2, or (at your option) any later version.
|
||||
|
||||
GDB, GAS, and the GNU binutils are distributed in the hope that they
|
||||
will be useful, but WITHOUT ANY WARRANTY; without even the implied
|
||||
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
|
||||
the GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this file; see the file COPYING. If not, write to the
|
||||
Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
|
||||
02110-1301, USA. */
|
||||
|
||||
struct ia64_opcode ia64_opcodes_d[] =
|
||||
{
|
||||
{"add", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_R1, IA64_OPND_IMM22, IA64_OPND_R3_2}, 0, 0, NULL},
|
||||
{"add", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_R1, IA64_OPND_IMM14, IA64_OPND_R3}, 0, 0, NULL},
|
||||
{"break", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_IMMU21}, 0, 0, NULL},
|
||||
{"chk.s", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_R2, IA64_OPND_TGT25b}, 0, 0, NULL},
|
||||
{"hint", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_IMMU21}, 0, 0, NULL},
|
||||
{"mov", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_R1, IA64_OPND_AR3}, 0, 0, NULL},
|
||||
{"mov", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_AR3, IA64_OPND_IMM8}, 0, 0, NULL},
|
||||
{"mov", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_AR3, IA64_OPND_R2}, 0, 0, NULL},
|
||||
{"nop", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_IMMU21}, 0, 0, NULL},
|
||||
{NULL, 0, 0, 0, 0, {0}, 0, 0, NULL}
|
||||
};
|
||||
@@ -1,656 +0,0 @@
|
||||
/* ia64-opc-f.c -- IA-64 `F' opcode table.
|
||||
Copyright 1998, 1999, 2000, 2002 Free Software Foundation, Inc.
|
||||
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
|
||||
|
||||
This file is part of GDB, GAS, and the GNU binutils.
|
||||
|
||||
GDB, GAS, and the GNU binutils are free software; you can redistribute
|
||||
them and/or modify them under the terms of the GNU General Public
|
||||
License as published by the Free Software Foundation; either version
|
||||
2, or (at your option) any later version.
|
||||
|
||||
GDB, GAS, and the GNU binutils are distributed in the hope that they
|
||||
will be useful, but WITHOUT ANY WARRANTY; without even the implied
|
||||
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
|
||||
the GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this file; see the file COPYING. If not, write to the
|
||||
Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
|
||||
02110-1301, USA. */
|
||||
|
||||
#include "ia64-opc.h"
|
||||
|
||||
#define f0 IA64_TYPE_F, 0
|
||||
#define f IA64_TYPE_F, 1
|
||||
#define f2 IA64_TYPE_F, 2
|
||||
|
||||
#define bF2(x) (((ia64_insn) ((x) & 0x7f)) << 13)
|
||||
#define bF4(x) (((ia64_insn) ((x) & 0x7f)) << 27)
|
||||
#define bQ(x) (((ia64_insn) ((x) & 0x1)) << 36)
|
||||
#define bRa(x) (((ia64_insn) ((x) & 0x1)) << 33)
|
||||
#define bRb(x) (((ia64_insn) ((x) & 0x1)) << 36)
|
||||
#define bSf(x) (((ia64_insn) ((x) & 0x3)) << 34)
|
||||
#define bTa(x) (((ia64_insn) ((x) & 0x1)) << 12)
|
||||
#define bXa(x) (((ia64_insn) ((x) & 0x1)) << 36)
|
||||
#define bXb(x) (((ia64_insn) ((x) & 0x1)) << 33)
|
||||
#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 34)
|
||||
#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27)
|
||||
#define bY(x) (((ia64_insn) ((x) & 0x1)) << 26)
|
||||
|
||||
#define mF2 bF2 (-1)
|
||||
#define mF4 bF4 (-1)
|
||||
#define mQ bQ (-1)
|
||||
#define mRa bRa (-1)
|
||||
#define mRb bRb (-1)
|
||||
#define mSf bSf (-1)
|
||||
#define mTa bTa (-1)
|
||||
#define mXa bXa (-1)
|
||||
#define mXb bXb (-1)
|
||||
#define mX2 bX2 (-1)
|
||||
#define mX6 bX6 (-1)
|
||||
#define mY bY (-1)
|
||||
|
||||
#define OpXa(a,b) (bOp (a) | bXa (b)), (mOp | mXa)
|
||||
#define OpXaSf(a,b,c) (bOp (a) | bXa (b) | bSf (c)), (mOp | mXa | mSf)
|
||||
#define OpXaSfF2(a,b,c,d) \
|
||||
(bOp (a) | bXa (b) | bSf (c) | bF2 (d)), (mOp | mXa | mSf | mF2)
|
||||
#define OpXaSfF4(a,b,c,d) \
|
||||
(bOp (a) | bXa (b) | bSf (c) | bF4 (d)), (mOp | mXa | mSf | mF4)
|
||||
#define OpXaSfF2F4(a,b,c,d,e) \
|
||||
(bOp (a) | bXa (b) | bSf (c) | bF2 (d) | bF4 (e)), \
|
||||
(mOp | mXa | mSf | mF2 | mF4)
|
||||
#define OpXaX2(a,b,c) (bOp (a) | bXa (b) | bX2 (c)), (mOp | mXa | mX2)
|
||||
#define OpXaX2F2(a,b,c,d) \
|
||||
(bOp (a) | bXa (b) | bX2 (c) | bF2 (d)), (mOp | mXa | mX2 | mF2)
|
||||
#define OpRaRbTaSf(a,b,c,d,e) \
|
||||
(bOp (a) | bRa (b) | bRb (c) | bTa (d) | bSf (e)), \
|
||||
(mOp | mRa | mRb | mTa | mSf)
|
||||
#define OpTa(a,b) (bOp (a) | bTa (b)), (mOp | mTa)
|
||||
#define OpXbQSf(a,b,c,d) \
|
||||
(bOp (a) | bXb (b) | bQ (c) | bSf (d)), (mOp | mXb | mQ | mSf)
|
||||
#define OpXbX6(a,b,c) \
|
||||
(bOp (a) | bXb (b) | bX6 (c)), (mOp | mXb | mX6)
|
||||
#define OpXbX6Y(a,b,c,d) \
|
||||
(bOp (a) | bXb (b) | bX6 (c) | bY (d)), (mOp | mXb | mX6 | mY)
|
||||
#define OpXbX6F2(a,b,c,d) \
|
||||
(bOp (a) | bXb (b) | bX6 (c) | bF2 (d)), (mOp | mXb | mX6 | mF2)
|
||||
#define OpXbX6Sf(a,b,c,d) \
|
||||
(bOp (a) | bXb (b) | bX6 (c) | bSf (d)), (mOp | mXb | mX6 | mSf)
|
||||
|
||||
/* Used to initialise unused fields in ia64_opcode struct,
|
||||
in order to stop gcc from complaining. */
|
||||
#define EMPTY 0,0,NULL
|
||||
|
||||
struct ia64_opcode ia64_opcodes_f[] =
|
||||
{
|
||||
/* F-type instruction encodings (sorted according to major opcode). */
|
||||
|
||||
{"frcpa.s0", f2, OpXbQSf (0, 1, 0, 0), {F1, P2, F2, F3}, EMPTY},
|
||||
{"frcpa", f2, OpXbQSf (0, 1, 0, 0), {F1, P2, F2, F3}, PSEUDO, 0, NULL},
|
||||
{"frcpa.s1", f2, OpXbQSf (0, 1, 0, 1), {F1, P2, F2, F3}, EMPTY},
|
||||
{"frcpa.s2", f2, OpXbQSf (0, 1, 0, 2), {F1, P2, F2, F3}, EMPTY},
|
||||
{"frcpa.s3", f2, OpXbQSf (0, 1, 0, 3), {F1, P2, F2, F3}, EMPTY},
|
||||
|
||||
{"frsqrta.s0", f2, OpXbQSf (0, 1, 1, 0), {F1, P2, F3}, EMPTY},
|
||||
{"frsqrta", f2, OpXbQSf (0, 1, 1, 0), {F1, P2, F3}, PSEUDO, 0, NULL},
|
||||
{"frsqrta.s1", f2, OpXbQSf (0, 1, 1, 1), {F1, P2, F3}, EMPTY},
|
||||
{"frsqrta.s2", f2, OpXbQSf (0, 1, 1, 2), {F1, P2, F3}, EMPTY},
|
||||
{"frsqrta.s3", f2, OpXbQSf (0, 1, 1, 3), {F1, P2, F3}, EMPTY},
|
||||
|
||||
{"fmin.s0", f, OpXbX6Sf (0, 0, 0x14, 0), {F1, F2, F3}, EMPTY},
|
||||
{"fmin", f, OpXbX6Sf (0, 0, 0x14, 0), {F1, F2, F3}, PSEUDO, 0, NULL},
|
||||
{"fmin.s1", f, OpXbX6Sf (0, 0, 0x14, 1), {F1, F2, F3}, EMPTY},
|
||||
{"fmin.s2", f, OpXbX6Sf (0, 0, 0x14, 2), {F1, F2, F3}, EMPTY},
|
||||
{"fmin.s3", f, OpXbX6Sf (0, 0, 0x14, 3), {F1, F2, F3}, EMPTY},
|
||||
{"fmax.s0", f, OpXbX6Sf (0, 0, 0x15, 0), {F1, F2, F3}, EMPTY},
|
||||
{"fmax", f, OpXbX6Sf (0, 0, 0x15, 0), {F1, F2, F3}, PSEUDO, 0, NULL},
|
||||
{"fmax.s1", f, OpXbX6Sf (0, 0, 0x15, 1), {F1, F2, F3}, EMPTY},
|
||||
{"fmax.s2", f, OpXbX6Sf (0, 0, 0x15, 2), {F1, F2, F3}, EMPTY},
|
||||
{"fmax.s3", f, OpXbX6Sf (0, 0, 0x15, 3), {F1, F2, F3}, EMPTY},
|
||||
{"famin.s0", f, OpXbX6Sf (0, 0, 0x16, 0), {F1, F2, F3}, EMPTY},
|
||||
{"famin", f, OpXbX6Sf (0, 0, 0x16, 0), {F1, F2, F3}, PSEUDO, 0, NULL},
|
||||
{"famin.s1", f, OpXbX6Sf (0, 0, 0x16, 1), {F1, F2, F3}, EMPTY},
|
||||
{"famin.s2", f, OpXbX6Sf (0, 0, 0x16, 2), {F1, F2, F3}, EMPTY},
|
||||
{"famin.s3", f, OpXbX6Sf (0, 0, 0x16, 3), {F1, F2, F3}, EMPTY},
|
||||
{"famax.s0", f, OpXbX6Sf (0, 0, 0x17, 0), {F1, F2, F3}, EMPTY},
|
||||
{"famax", f, OpXbX6Sf (0, 0, 0x17, 0), {F1, F2, F3}, PSEUDO, 0, NULL},
|
||||
{"famax.s1", f, OpXbX6Sf (0, 0, 0x17, 1), {F1, F2, F3}, EMPTY},
|
||||
{"famax.s2", f, OpXbX6Sf (0, 0, 0x17, 2), {F1, F2, F3}, EMPTY},
|
||||
{"famax.s3", f, OpXbX6Sf (0, 0, 0x17, 3), {F1, F2, F3}, EMPTY},
|
||||
|
||||
{"mov", f, OpXbX6 (0, 0, 0x10), {F1, F3}, PSEUDO | F2_EQ_F3, 0, NULL},
|
||||
{"fabs", f, OpXbX6F2 (0, 0, 0x10, 0), {F1, F3}, PSEUDO, 0, NULL},
|
||||
{"fneg", f, OpXbX6 (0, 0, 0x11), {F1, F3}, PSEUDO | F2_EQ_F3, 0, NULL},
|
||||
{"fnegabs", f, OpXbX6F2 (0, 0, 0x11, 0), {F1, F3}, PSEUDO, 0, NULL},
|
||||
{"fmerge.s", f, OpXbX6 (0, 0, 0x10), {F1, F2, F3}, EMPTY},
|
||||
{"fmerge.ns", f, OpXbX6 (0, 0, 0x11), {F1, F2, F3}, EMPTY},
|
||||
|
||||
{"fmerge.se", f, OpXbX6 (0, 0, 0x12), {F1, F2, F3}, EMPTY},
|
||||
{"fmix.lr", f, OpXbX6 (0, 0, 0x39), {F1, F2, F3}, EMPTY},
|
||||
{"fmix.r", f, OpXbX6 (0, 0, 0x3a), {F1, F2, F3}, EMPTY},
|
||||
{"fmix.l", f, OpXbX6 (0, 0, 0x3b), {F1, F2, F3}, EMPTY},
|
||||
{"fsxt.r", f, OpXbX6 (0, 0, 0x3c), {F1, F2, F3}, EMPTY},
|
||||
{"fsxt.l", f, OpXbX6 (0, 0, 0x3d), {F1, F2, F3}, EMPTY},
|
||||
{"fpack", f, OpXbX6 (0, 0, 0x28), {F1, F2, F3}, EMPTY},
|
||||
{"fswap", f, OpXbX6 (0, 0, 0x34), {F1, F2, F3}, EMPTY},
|
||||
{"fswap.nl", f, OpXbX6 (0, 0, 0x35), {F1, F2, F3}, EMPTY},
|
||||
{"fswap.nr", f, OpXbX6 (0, 0, 0x36), {F1, F2, F3}, EMPTY},
|
||||
{"fand", f, OpXbX6 (0, 0, 0x2c), {F1, F2, F3}, EMPTY},
|
||||
{"fandcm", f, OpXbX6 (0, 0, 0x2d), {F1, F2, F3}, EMPTY},
|
||||
{"for", f, OpXbX6 (0, 0, 0x2e), {F1, F2, F3}, EMPTY},
|
||||
{"fxor", f, OpXbX6 (0, 0, 0x2f), {F1, F2, F3}, EMPTY},
|
||||
|
||||
{"fcvt.fx.s0", f, OpXbX6Sf (0, 0, 0x18, 0), {F1, F2}, EMPTY},
|
||||
{"fcvt.fx", f, OpXbX6Sf (0, 0, 0x18, 0), {F1, F2}, PSEUDO, 0, NULL},
|
||||
{"fcvt.fx.s1", f, OpXbX6Sf (0, 0, 0x18, 1), {F1, F2}, EMPTY},
|
||||
{"fcvt.fx.s2", f, OpXbX6Sf (0, 0, 0x18, 2), {F1, F2}, EMPTY},
|
||||
{"fcvt.fx.s3", f, OpXbX6Sf (0, 0, 0x18, 3), {F1, F2}, EMPTY},
|
||||
{"fcvt.fxu.s0", f, OpXbX6Sf (0, 0, 0x19, 0), {F1, F2}, EMPTY},
|
||||
{"fcvt.fxu", f, OpXbX6Sf (0, 0, 0x19, 0), {F1, F2}, PSEUDO, 0, NULL},
|
||||
{"fcvt.fxu.s1", f, OpXbX6Sf (0, 0, 0x19, 1), {F1, F2}, EMPTY},
|
||||
{"fcvt.fxu.s2", f, OpXbX6Sf (0, 0, 0x19, 2), {F1, F2}, EMPTY},
|
||||
{"fcvt.fxu.s3", f, OpXbX6Sf (0, 0, 0x19, 3), {F1, F2}, EMPTY},
|
||||
{"fcvt.fx.trunc.s0", f, OpXbX6Sf (0, 0, 0x1a, 0), {F1, F2}, EMPTY},
|
||||
{"fcvt.fx.trunc", f, OpXbX6Sf (0, 0, 0x1a, 0), {F1, F2}, PSEUDO, 0, NULL},
|
||||
{"fcvt.fx.trunc.s1", f, OpXbX6Sf (0, 0, 0x1a, 1), {F1, F2}, EMPTY},
|
||||
{"fcvt.fx.trunc.s2", f, OpXbX6Sf (0, 0, 0x1a, 2), {F1, F2}, EMPTY},
|
||||
{"fcvt.fx.trunc.s3", f, OpXbX6Sf (0, 0, 0x1a, 3), {F1, F2}, EMPTY},
|
||||
{"fcvt.fxu.trunc.s0", f, OpXbX6Sf (0, 0, 0x1b, 0), {F1, F2}, EMPTY},
|
||||
{"fcvt.fxu.trunc", f, OpXbX6Sf (0, 0, 0x1b, 0), {F1, F2}, PSEUDO, 0, NULL},
|
||||
{"fcvt.fxu.trunc.s1", f, OpXbX6Sf (0, 0, 0x1b, 1), {F1, F2}, EMPTY},
|
||||
{"fcvt.fxu.trunc.s2", f, OpXbX6Sf (0, 0, 0x1b, 2), {F1, F2}, EMPTY},
|
||||
{"fcvt.fxu.trunc.s3", f, OpXbX6Sf (0, 0, 0x1b, 3), {F1, F2}, EMPTY},
|
||||
|
||||
{"fcvt.xf", f, OpXbX6 (0, 0, 0x1c), {F1, F2}, EMPTY},
|
||||
|
||||
{"fsetc.s0", f0, OpXbX6Sf (0, 0, 0x04, 0), {IMMU7a, IMMU7b}, EMPTY},
|
||||
{"fsetc", f0, OpXbX6Sf (0, 0, 0x04, 0), {IMMU7a, IMMU7b}, PSEUDO, 0, NULL},
|
||||
{"fsetc.s1", f0, OpXbX6Sf (0, 0, 0x04, 1), {IMMU7a, IMMU7b}, EMPTY},
|
||||
{"fsetc.s2", f0, OpXbX6Sf (0, 0, 0x04, 2), {IMMU7a, IMMU7b}, EMPTY},
|
||||
{"fsetc.s3", f0, OpXbX6Sf (0, 0, 0x04, 3), {IMMU7a, IMMU7b}, EMPTY},
|
||||
{"fclrf.s0", f0, OpXbX6Sf (0, 0, 0x05, 0), {}, EMPTY},
|
||||
{"fclrf", f0, OpXbX6Sf (0, 0, 0x05, 0), {0}, PSEUDO, 0, NULL},
|
||||
{"fclrf.s1", f0, OpXbX6Sf (0, 0, 0x05, 1), {}, EMPTY},
|
||||
{"fclrf.s2", f0, OpXbX6Sf (0, 0, 0x05, 2), {}, EMPTY},
|
||||
{"fclrf.s3", f0, OpXbX6Sf (0, 0, 0x05, 3), {}, EMPTY},
|
||||
{"fchkf.s0", f0, OpXbX6Sf (0, 0, 0x08, 0), {TGT25}, EMPTY},
|
||||
{"fchkf", f0, OpXbX6Sf (0, 0, 0x08, 0), {TGT25}, PSEUDO, 0, NULL},
|
||||
{"fchkf.s1", f0, OpXbX6Sf (0, 0, 0x08, 1), {TGT25}, EMPTY},
|
||||
{"fchkf.s2", f0, OpXbX6Sf (0, 0, 0x08, 2), {TGT25}, EMPTY},
|
||||
{"fchkf.s3", f0, OpXbX6Sf (0, 0, 0x08, 3), {TGT25}, EMPTY},
|
||||
|
||||
{"break.f", f0, OpXbX6 (0, 0, 0x00), {IMMU21}, EMPTY},
|
||||
{"nop.f", f0, OpXbX6Y (0, 0, 0x01, 0), {IMMU21}, EMPTY},
|
||||
{"hint.f", f0, OpXbX6Y (0, 0, 0x01, 1), {IMMU21}, EMPTY},
|
||||
|
||||
{"fprcpa.s0", f2, OpXbQSf (1, 1, 0, 0), {F1, P2, F2, F3}, EMPTY},
|
||||
{"fprcpa", f2, OpXbQSf (1, 1, 0, 0), {F1, P2, F2, F3}, PSEUDO, 0, NULL},
|
||||
{"fprcpa.s1", f2, OpXbQSf (1, 1, 0, 1), {F1, P2, F2, F3}, EMPTY},
|
||||
{"fprcpa.s2", f2, OpXbQSf (1, 1, 0, 2), {F1, P2, F2, F3}, EMPTY},
|
||||
{"fprcpa.s3", f2, OpXbQSf (1, 1, 0, 3), {F1, P2, F2, F3}, EMPTY},
|
||||
|
||||
{"fprsqrta.s0", f2, OpXbQSf (1, 1, 1, 0), {F1, P2, F3}, EMPTY},
|
||||
{"fprsqrta", f2, OpXbQSf (1, 1, 1, 0), {F1, P2, F3}, PSEUDO, 0, NULL},
|
||||
{"fprsqrta.s1", f2, OpXbQSf (1, 1, 1, 1), {F1, P2, F3}, EMPTY},
|
||||
{"fprsqrta.s2", f2, OpXbQSf (1, 1, 1, 2), {F1, P2, F3}, EMPTY},
|
||||
{"fprsqrta.s3", f2, OpXbQSf (1, 1, 1, 3), {F1, P2, F3}, EMPTY},
|
||||
|
||||
{"fpmin.s0", f, OpXbX6Sf (1, 0, 0x14, 0), {F1, F2, F3}, EMPTY},
|
||||
{"fpmin", f, OpXbX6Sf (1, 0, 0x14, 0), {F1, F2, F3}, PSEUDO, 0, NULL},
|
||||
{"fpmin.s1", f, OpXbX6Sf (1, 0, 0x14, 1), {F1, F2, F3}, EMPTY},
|
||||
{"fpmin.s2", f, OpXbX6Sf (1, 0, 0x14, 2), {F1, F2, F3}, EMPTY},
|
||||
{"fpmin.s3", f, OpXbX6Sf (1, 0, 0x14, 3), {F1, F2, F3}, EMPTY},
|
||||
{"fpmax.s0", f, OpXbX6Sf (1, 0, 0x15, 0), {F1, F2, F3}, EMPTY},
|
||||
{"fpmax", f, OpXbX6Sf (1, 0, 0x15, 0), {F1, F2, F3}, PSEUDO, 0, NULL},
|
||||
{"fpmax.s1", f, OpXbX6Sf (1, 0, 0x15, 1), {F1, F2, F3}, EMPTY},
|
||||
{"fpmax.s2", f, OpXbX6Sf (1, 0, 0x15, 2), {F1, F2, F3}, EMPTY},
|
||||
{"fpmax.s3", f, OpXbX6Sf (1, 0, 0x15, 3), {F1, F2, F3}, EMPTY},
|
||||
{"fpamin.s0", f, OpXbX6Sf (1, 0, 0x16, 0), {F1, F2, F3}, EMPTY},
|
||||
{"fpamin", f, OpXbX6Sf (1, 0, 0x16, 0), {F1, F2, F3}, PSEUDO, 0, NULL},
|
||||
{"fpamin.s1", f, OpXbX6Sf (1, 0, 0x16, 1), {F1, F2, F3}, EMPTY},
|
||||
{"fpamin.s2", f, OpXbX6Sf (1, 0, 0x16, 2), {F1, F2, F3}, EMPTY},
|
||||
{"fpamin.s3", f, OpXbX6Sf (1, 0, 0x16, 3), {F1, F2, F3}, EMPTY},
|
||||
{"fpamax.s0", f, OpXbX6Sf (1, 0, 0x17, 0), {F1, F2, F3}, EMPTY},
|
||||
{"fpamax", f, OpXbX6Sf (1, 0, 0x17, 0), {F1, F2, F3}, PSEUDO, 0, NULL},
|
||||
{"fpamax.s1", f, OpXbX6Sf (1, 0, 0x17, 1), {F1, F2, F3}, EMPTY},
|
||||
{"fpamax.s2", f, OpXbX6Sf (1, 0, 0x17, 2), {F1, F2, F3}, EMPTY},
|
||||
{"fpamax.s3", f, OpXbX6Sf (1, 0, 0x17, 3), {F1, F2, F3}, EMPTY},
|
||||
|
||||
{"fpcmp.eq.s0", f, OpXbX6Sf (1, 0, 0x30, 0), {F1, F2, F3}, EMPTY},
|
||||
{"fpcmp.eq", f, OpXbX6Sf (1, 0, 0x30, 0), {F1, F2, F3}, PSEUDO, 0, NULL},
|
||||
{"fpcmp.eq.s1", f, OpXbX6Sf (1, 0, 0x30, 1), {F1, F2, F3}, EMPTY},
|
||||
{"fpcmp.eq.s2", f, OpXbX6Sf (1, 0, 0x30, 2), {F1, F2, F3}, EMPTY},
|
||||
{"fpcmp.eq.s3", f, OpXbX6Sf (1, 0, 0x30, 3), {F1, F2, F3}, EMPTY},
|
||||
{"fpcmp.lt.s0", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F2, F3}, EMPTY},
|
||||
{"fpcmp.lt", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F2, F3}, PSEUDO, 0, NULL},
|
||||
{"fpcmp.lt.s1", f, OpXbX6Sf (1, 0, 0x31, 1), {F1, F2, F3}, EMPTY},
|
||||
{"fpcmp.lt.s2", f, OpXbX6Sf (1, 0, 0x31, 2), {F1, F2, F3}, EMPTY},
|
||||
{"fpcmp.lt.s3", f, OpXbX6Sf (1, 0, 0x31, 3), {F1, F2, F3}, EMPTY},
|
||||
{"fpcmp.le.s0", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F2, F3}, EMPTY},
|
||||
{"fpcmp.le", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F2, F3}, PSEUDO, 0, NULL},
|
||||
{"fpcmp.le.s1", f, OpXbX6Sf (1, 0, 0x32, 1), {F1, F2, F3}, EMPTY},
|
||||
{"fpcmp.le.s2", f, OpXbX6Sf (1, 0, 0x32, 2), {F1, F2, F3}, EMPTY},
|
||||
{"fpcmp.le.s3", f, OpXbX6Sf (1, 0, 0x32, 3), {F1, F2, F3}, EMPTY},
|
||||
{"fpcmp.gt.s0", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fpcmp.gt", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fpcmp.gt.s1", f, OpXbX6Sf (1, 0, 0x31, 1), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fpcmp.gt.s2", f, OpXbX6Sf (1, 0, 0x31, 2), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fpcmp.gt.s3", f, OpXbX6Sf (1, 0, 0x31, 3), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fpcmp.ge.s0", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fpcmp.ge", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fpcmp.ge.s1", f, OpXbX6Sf (1, 0, 0x32, 1), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fpcmp.ge.s2", f, OpXbX6Sf (1, 0, 0x32, 2), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fpcmp.ge.s3", f, OpXbX6Sf (1, 0, 0x32, 3), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fpcmp.unord.s0", f, OpXbX6Sf (1, 0, 0x33, 0), {F1, F2, F3}, EMPTY},
|
||||
{"fpcmp.unord", f, OpXbX6Sf (1, 0, 0x33, 0), {F1, F2, F3}, PSEUDO, 0, NULL},
|
||||
{"fpcmp.unord.s1", f, OpXbX6Sf (1, 0, 0x33, 1), {F1, F2, F3}, EMPTY},
|
||||
{"fpcmp.unord.s2", f, OpXbX6Sf (1, 0, 0x33, 2), {F1, F2, F3}, EMPTY},
|
||||
{"fpcmp.unord.s3", f, OpXbX6Sf (1, 0, 0x33, 3), {F1, F2, F3}, EMPTY},
|
||||
{"fpcmp.neq.s0", f, OpXbX6Sf (1, 0, 0x34, 0), {F1, F2, F3}, EMPTY},
|
||||
{"fpcmp.neq", f, OpXbX6Sf (1, 0, 0x34, 0), {F1, F2, F3}, PSEUDO, 0, NULL},
|
||||
{"fpcmp.neq.s1", f, OpXbX6Sf (1, 0, 0x34, 1), {F1, F2, F3}, EMPTY},
|
||||
{"fpcmp.neq.s2", f, OpXbX6Sf (1, 0, 0x34, 2), {F1, F2, F3}, EMPTY},
|
||||
{"fpcmp.neq.s3", f, OpXbX6Sf (1, 0, 0x34, 3), {F1, F2, F3}, EMPTY},
|
||||
{"fpcmp.nlt.s0", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F2, F3}, EMPTY},
|
||||
{"fpcmp.nlt", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F2, F3}, PSEUDO, 0, NULL},
|
||||
{"fpcmp.nlt.s1", f, OpXbX6Sf (1, 0, 0x35, 1), {F1, F2, F3}, EMPTY},
|
||||
{"fpcmp.nlt.s2", f, OpXbX6Sf (1, 0, 0x35, 2), {F1, F2, F3}, EMPTY},
|
||||
{"fpcmp.nlt.s3", f, OpXbX6Sf (1, 0, 0x35, 3), {F1, F2, F3}, EMPTY},
|
||||
{"fpcmp.nle.s0", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F2, F3}, EMPTY},
|
||||
{"fpcmp.nle", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F2, F3}, PSEUDO, 0, NULL},
|
||||
{"fpcmp.nle.s1", f, OpXbX6Sf (1, 0, 0x36, 1), {F1, F2, F3}, EMPTY},
|
||||
{"fpcmp.nle.s2", f, OpXbX6Sf (1, 0, 0x36, 2), {F1, F2, F3}, EMPTY},
|
||||
{"fpcmp.nle.s3", f, OpXbX6Sf (1, 0, 0x36, 3), {F1, F2, F3}, EMPTY},
|
||||
{"fpcmp.ngt.s0", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fpcmp.ngt", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fpcmp.ngt.s1", f, OpXbX6Sf (1, 0, 0x35, 1), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fpcmp.ngt.s2", f, OpXbX6Sf (1, 0, 0x35, 2), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fpcmp.ngt.s3", f, OpXbX6Sf (1, 0, 0x35, 3), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fpcmp.nge.s0", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fpcmp.nge", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fpcmp.nge.s1", f, OpXbX6Sf (1, 0, 0x36, 1), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fpcmp.nge.s2", f, OpXbX6Sf (1, 0, 0x36, 2), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fpcmp.nge.s3", f, OpXbX6Sf (1, 0, 0x36, 3), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fpcmp.ord.s0", f, OpXbX6Sf (1, 0, 0x37, 0), {F1, F2, F3}, EMPTY},
|
||||
{"fpcmp.ord", f, OpXbX6Sf (1, 0, 0x37, 0), {F1, F2, F3}, PSEUDO, 0, NULL},
|
||||
{"fpcmp.ord.s1", f, OpXbX6Sf (1, 0, 0x37, 1), {F1, F2, F3}, EMPTY},
|
||||
{"fpcmp.ord.s2", f, OpXbX6Sf (1, 0, 0x37, 2), {F1, F2, F3}, EMPTY},
|
||||
{"fpcmp.ord.s3", f, OpXbX6Sf (1, 0, 0x37, 3), {F1, F2, F3}, EMPTY},
|
||||
|
||||
{"fpabs", f, OpXbX6F2 (1, 0, 0x10, 0), {F1, F3}, PSEUDO, 0, NULL},
|
||||
{"fpneg", f, OpXbX6 (1, 0, 0x11), {F1, F3}, PSEUDO | F2_EQ_F3, 0, NULL},
|
||||
{"fpnegabs", f, OpXbX6F2 (1, 0, 0x11, 0), {F1, F3}, PSEUDO, 0, NULL},
|
||||
{"fpmerge.s", f, OpXbX6 (1, 0, 0x10), {F1, F2, F3}, EMPTY},
|
||||
{"fpmerge.ns", f, OpXbX6 (1, 0, 0x11), {F1, F2, F3}, EMPTY},
|
||||
{"fpmerge.se", f, OpXbX6 (1, 0, 0x12), {F1, F2, F3}, EMPTY},
|
||||
|
||||
{"fpcvt.fx.s0", f, OpXbX6Sf (1, 0, 0x18, 0), {F1, F2}, EMPTY},
|
||||
{"fpcvt.fx", f, OpXbX6Sf (1, 0, 0x18, 0), {F1, F2}, PSEUDO, 0, NULL},
|
||||
{"fpcvt.fx.s1", f, OpXbX6Sf (1, 0, 0x18, 1), {F1, F2}, EMPTY},
|
||||
{"fpcvt.fx.s2", f, OpXbX6Sf (1, 0, 0x18, 2), {F1, F2}, EMPTY},
|
||||
{"fpcvt.fx.s3", f, OpXbX6Sf (1, 0, 0x18, 3), {F1, F2}, EMPTY},
|
||||
{"fpcvt.fxu.s0", f, OpXbX6Sf (1, 0, 0x19, 0), {F1, F2}, EMPTY},
|
||||
{"fpcvt.fxu", f, OpXbX6Sf (1, 0, 0x19, 0), {F1, F2}, PSEUDO, 0, NULL},
|
||||
{"fpcvt.fxu.s1", f, OpXbX6Sf (1, 0, 0x19, 1), {F1, F2}, EMPTY},
|
||||
{"fpcvt.fxu.s2", f, OpXbX6Sf (1, 0, 0x19, 2), {F1, F2}, EMPTY},
|
||||
{"fpcvt.fxu.s3", f, OpXbX6Sf (1, 0, 0x19, 3), {F1, F2}, EMPTY},
|
||||
{"fpcvt.fx.trunc.s0", f, OpXbX6Sf (1, 0, 0x1a, 0), {F1, F2}, EMPTY},
|
||||
{"fpcvt.fx.trunc", f, OpXbX6Sf (1, 0, 0x1a, 0), {F1, F2}, PSEUDO, 0, NULL},
|
||||
{"fpcvt.fx.trunc.s1", f, OpXbX6Sf (1, 0, 0x1a, 1), {F1, F2}, EMPTY},
|
||||
{"fpcvt.fx.trunc.s2", f, OpXbX6Sf (1, 0, 0x1a, 2), {F1, F2}, EMPTY},
|
||||
{"fpcvt.fx.trunc.s3", f, OpXbX6Sf (1, 0, 0x1a, 3), {F1, F2}, EMPTY},
|
||||
{"fpcvt.fxu.trunc.s0", f, OpXbX6Sf (1, 0, 0x1b, 0), {F1, F2}, EMPTY},
|
||||
{"fpcvt.fxu.trunc", f, OpXbX6Sf (1, 0, 0x1b, 0), {F1, F2}, PSEUDO, 0, NULL},
|
||||
{"fpcvt.fxu.trunc.s1", f, OpXbX6Sf (1, 0, 0x1b, 1), {F1, F2}, EMPTY},
|
||||
{"fpcvt.fxu.trunc.s2", f, OpXbX6Sf (1, 0, 0x1b, 2), {F1, F2}, EMPTY},
|
||||
{"fpcvt.fxu.trunc.s3", f, OpXbX6Sf (1, 0, 0x1b, 3), {F1, F2}, EMPTY},
|
||||
|
||||
{"fcmp.eq.s0", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P1, P2, F2, F3}, EMPTY},
|
||||
{"fcmp.eq", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P1, P2, F2, F3}, PSEUDO, 0, NULL},
|
||||
{"fcmp.eq.s1", f2, OpRaRbTaSf (4, 0, 0, 0, 1), {P1, P2, F2, F3}, EMPTY},
|
||||
{"fcmp.eq.s2", f2, OpRaRbTaSf (4, 0, 0, 0, 2), {P1, P2, F2, F3}, EMPTY},
|
||||
{"fcmp.eq.s3", f2, OpRaRbTaSf (4, 0, 0, 0, 3), {P1, P2, F2, F3}, EMPTY},
|
||||
{"fcmp.lt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F2, F3}, EMPTY},
|
||||
{"fcmp.lt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F2, F3}, PSEUDO, 0, NULL},
|
||||
{"fcmp.lt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P1, P2, F2, F3}, EMPTY},
|
||||
{"fcmp.lt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P1, P2, F2, F3}, EMPTY},
|
||||
{"fcmp.lt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P1, P2, F2, F3}, EMPTY},
|
||||
{"fcmp.le.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F2, F3}, EMPTY},
|
||||
{"fcmp.le", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F2, F3}, PSEUDO, 0, NULL},
|
||||
{"fcmp.le.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P1, P2, F2, F3}, EMPTY},
|
||||
{"fcmp.le.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P1, P2, F2, F3}, EMPTY},
|
||||
{"fcmp.le.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P1, P2, F2, F3}, EMPTY},
|
||||
{"fcmp.unord.s0", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P1, P2, F2, F3}, EMPTY},
|
||||
{"fcmp.unord", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P1, P2, F2, F3}, PSEUDO, 0, NULL},
|
||||
{"fcmp.unord.s1", f2, OpRaRbTaSf (4, 1, 1, 0, 1), {P1, P2, F2, F3}, EMPTY},
|
||||
{"fcmp.unord.s2", f2, OpRaRbTaSf (4, 1, 1, 0, 2), {P1, P2, F2, F3}, EMPTY},
|
||||
{"fcmp.unord.s3", f2, OpRaRbTaSf (4, 1, 1, 0, 3), {P1, P2, F2, F3}, EMPTY},
|
||||
{"fcmp.eq.unc.s0", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P1, P2, F2, F3}, EMPTY},
|
||||
{"fcmp.eq.unc", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P1, P2, F2, F3}, PSEUDO, 0, NULL},
|
||||
{"fcmp.eq.unc.s1", f2, OpRaRbTaSf (4, 0, 0, 1, 1), {P1, P2, F2, F3}, EMPTY},
|
||||
{"fcmp.eq.unc.s2", f2, OpRaRbTaSf (4, 0, 0, 1, 2), {P1, P2, F2, F3}, EMPTY},
|
||||
{"fcmp.eq.unc.s3", f2, OpRaRbTaSf (4, 0, 0, 1, 3), {P1, P2, F2, F3}, EMPTY},
|
||||
{"fcmp.lt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F2, F3}, EMPTY},
|
||||
{"fcmp.lt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F2, F3}, PSEUDO, 0, NULL},
|
||||
{"fcmp.lt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P1, P2, F2, F3}, EMPTY},
|
||||
{"fcmp.lt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P1, P2, F2, F3}, EMPTY},
|
||||
{"fcmp.lt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P1, P2, F2, F3}, EMPTY},
|
||||
{"fcmp.le.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F2, F3}, EMPTY},
|
||||
{"fcmp.le.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F2, F3}, PSEUDO, 0, NULL},
|
||||
{"fcmp.le.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P1, P2, F2, F3}, EMPTY},
|
||||
{"fcmp.le.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P1, P2, F2, F3}, EMPTY},
|
||||
{"fcmp.le.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P1, P2, F2, F3}, EMPTY},
|
||||
{"fcmp.unord.unc.s0", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P1, P2, F2, F3}, EMPTY},
|
||||
{"fcmp.unord.unc", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P1, P2, F2, F3}, PSEUDO, 0, NULL},
|
||||
{"fcmp.unord.unc.s1", f2, OpRaRbTaSf (4, 1, 1, 1, 1), {P1, P2, F2, F3}, EMPTY},
|
||||
{"fcmp.unord.unc.s2", f2, OpRaRbTaSf (4, 1, 1, 1, 2), {P1, P2, F2, F3}, EMPTY},
|
||||
{"fcmp.unord.unc.s3", f2, OpRaRbTaSf (4, 1, 1, 1, 3), {P1, P2, F2, F3}, EMPTY},
|
||||
|
||||
/* pseudo-ops of the above */
|
||||
{"fcmp.gt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F3, F2}, EMPTY},
|
||||
{"fcmp.gt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fcmp.gt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P1, P2, F3, F2}, EMPTY},
|
||||
{"fcmp.gt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P1, P2, F3, F2}, EMPTY},
|
||||
{"fcmp.gt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P1, P2, F3, F2}, EMPTY},
|
||||
{"fcmp.ge.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F3, F2}, EMPTY},
|
||||
{"fcmp.ge", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fcmp.ge.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P1, P2, F3, F2}, EMPTY},
|
||||
{"fcmp.ge.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P1, P2, F3, F2}, EMPTY},
|
||||
{"fcmp.ge.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P1, P2, F3, F2}, EMPTY},
|
||||
{"fcmp.neq.s0", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P2, P1, F2, F3}, EMPTY},
|
||||
{"fcmp.neq", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P2, P1, F2, F3}, PSEUDO, 0, NULL},
|
||||
{"fcmp.neq.s1", f2, OpRaRbTaSf (4, 0, 0, 0, 1), {P2, P1, F2, F3}, EMPTY},
|
||||
{"fcmp.neq.s2", f2, OpRaRbTaSf (4, 0, 0, 0, 2), {P2, P1, F2, F3}, EMPTY},
|
||||
{"fcmp.neq.s3", f2, OpRaRbTaSf (4, 0, 0, 0, 3), {P2, P1, F2, F3}, EMPTY},
|
||||
{"fcmp.nlt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F2, F3}, EMPTY},
|
||||
{"fcmp.nlt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F2, F3}, PSEUDO, 0, NULL},
|
||||
{"fcmp.nlt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P2, P1, F2, F3}, EMPTY},
|
||||
{"fcmp.nlt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P2, P1, F2, F3}, EMPTY},
|
||||
{"fcmp.nlt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P2, P1, F2, F3}, EMPTY},
|
||||
{"fcmp.nle.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F2, F3}, EMPTY},
|
||||
{"fcmp.nle", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F2, F3}, PSEUDO, 0, NULL},
|
||||
{"fcmp.nle.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P2, P1, F2, F3}, EMPTY},
|
||||
{"fcmp.nle.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P2, P1, F2, F3}, EMPTY},
|
||||
{"fcmp.nle.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P2, P1, F2, F3}, EMPTY},
|
||||
{"fcmp.ngt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F3, F2}, EMPTY},
|
||||
{"fcmp.ngt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fcmp.ngt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P2, P1, F3, F2}, EMPTY},
|
||||
{"fcmp.ngt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P2, P1, F3, F2}, EMPTY},
|
||||
{"fcmp.ngt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P2, P1, F3, F2}, EMPTY},
|
||||
{"fcmp.nge.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F3, F2}, EMPTY},
|
||||
{"fcmp.nge", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fcmp.nge.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P2, P1, F3, F2}, EMPTY},
|
||||
{"fcmp.nge.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P2, P1, F3, F2}, EMPTY},
|
||||
{"fcmp.nge.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P2, P1, F3, F2}, EMPTY},
|
||||
{"fcmp.ord.s0", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P2, P1, F2, F3}, EMPTY},
|
||||
{"fcmp.ord", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P2, P1, F2, F3}, PSEUDO, 0, NULL},
|
||||
{"fcmp.ord.s1", f2, OpRaRbTaSf (4, 1, 1, 0, 1), {P2, P1, F2, F3}, EMPTY},
|
||||
{"fcmp.ord.s2", f2, OpRaRbTaSf (4, 1, 1, 0, 2), {P2, P1, F2, F3}, EMPTY},
|
||||
{"fcmp.ord.s3", f2, OpRaRbTaSf (4, 1, 1, 0, 3), {P2, P1, F2, F3}, EMPTY},
|
||||
{"fcmp.gt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F3, F2}, EMPTY},
|
||||
{"fcmp.gt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fcmp.gt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P1, P2, F3, F2}, EMPTY},
|
||||
{"fcmp.gt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P1, P2, F3, F2}, EMPTY},
|
||||
{"fcmp.gt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P1, P2, F3, F2}, EMPTY},
|
||||
{"fcmp.ge.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F3, F2}, EMPTY},
|
||||
{"fcmp.ge.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fcmp.ge.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P1, P2, F3, F2}, EMPTY},
|
||||
{"fcmp.ge.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P1, P2, F3, F2}, EMPTY},
|
||||
{"fcmp.ge.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P1, P2, F3, F2}, EMPTY},
|
||||
{"fcmp.neq.unc.s0", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P2, P1, F2, F3}, EMPTY},
|
||||
{"fcmp.neq.unc", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P2, P1, F2, F3}, PSEUDO, 0, NULL},
|
||||
{"fcmp.neq.unc.s1", f2, OpRaRbTaSf (4, 0, 0, 1, 1), {P2, P1, F2, F3}, EMPTY},
|
||||
{"fcmp.neq.unc.s2", f2, OpRaRbTaSf (4, 0, 0, 1, 2), {P2, P1, F2, F3}, EMPTY},
|
||||
{"fcmp.neq.unc.s3", f2, OpRaRbTaSf (4, 0, 0, 1, 3), {P2, P1, F2, F3}, EMPTY},
|
||||
{"fcmp.nlt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F2, F3}, EMPTY},
|
||||
{"fcmp.nlt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F2, F3}, PSEUDO, 0, NULL},
|
||||
{"fcmp.nlt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P2, P1, F2, F3}, EMPTY},
|
||||
{"fcmp.nlt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P2, P1, F2, F3}, EMPTY},
|
||||
{"fcmp.nlt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P2, P1, F2, F3}, EMPTY},
|
||||
{"fcmp.nle.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F2, F3}, EMPTY},
|
||||
{"fcmp.nle.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F2, F3}, PSEUDO, 0, NULL},
|
||||
{"fcmp.nle.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P2, P1, F2, F3}, EMPTY},
|
||||
{"fcmp.nle.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P2, P1, F2, F3}, EMPTY},
|
||||
{"fcmp.nle.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P2, P1, F2, F3}, EMPTY},
|
||||
{"fcmp.ngt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F3, F2}, EMPTY},
|
||||
{"fcmp.ngt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fcmp.ngt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P2, P1, F3, F2}, EMPTY},
|
||||
{"fcmp.ngt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P2, P1, F3, F2}, EMPTY},
|
||||
{"fcmp.ngt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P2, P1, F3, F2}, EMPTY},
|
||||
{"fcmp.nge.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F3, F2}, EMPTY},
|
||||
{"fcmp.nge.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fcmp.nge.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P2, P1, F3, F2}, EMPTY},
|
||||
{"fcmp.nge.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P2, P1, F3, F2}, EMPTY},
|
||||
{"fcmp.nge.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P2, P1, F3, F2}, EMPTY},
|
||||
{"fcmp.ord.unc.s0", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P2, P1, F2, F3}, EMPTY},
|
||||
{"fcmp.ord.unc", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P2, P1, F2, F3}, PSEUDO, 0, NULL},
|
||||
{"fcmp.ord.unc.s1", f2, OpRaRbTaSf (4, 1, 1, 1, 1), {P2, P1, F2, F3}, EMPTY},
|
||||
{"fcmp.ord.unc.s2", f2, OpRaRbTaSf (4, 1, 1, 1, 2), {P2, P1, F2, F3}, EMPTY},
|
||||
{"fcmp.ord.unc.s3", f2, OpRaRbTaSf (4, 1, 1, 1, 3), {P2, P1, F2, F3}, EMPTY},
|
||||
|
||||
{"fclass.m", f2, OpTa (5, 0), {P1, P2, F2, IMMU9}, EMPTY},
|
||||
{"fclass.nm", f2, OpTa (5, 0), {P2, P1, F2, IMMU9}, PSEUDO, 0, NULL},
|
||||
{"fclass.m.unc", f2, OpTa (5, 1), {P1, P2, F2, IMMU9}, EMPTY},
|
||||
{"fclass.nm.unc", f2, OpTa (5, 1), {P2, P1, F2, IMMU9}, PSEUDO, 0, NULL},
|
||||
|
||||
/* note: fnorm and fcvt.xuf have identical encodings! */
|
||||
{"fnorm.s0", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL},
|
||||
{"fnorm", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL},
|
||||
{"fnorm.s1", f, OpXaSfF2F4 (0x8, 0, 1, 0, 1), {F1, F3}, PSEUDO, 0, NULL},
|
||||
{"fnorm.s2", f, OpXaSfF2F4 (0x8, 0, 2, 0, 1), {F1, F3}, PSEUDO, 0, NULL},
|
||||
{"fnorm.s3", f, OpXaSfF2F4 (0x8, 0, 3, 0, 1), {F1, F3}, PSEUDO, 0, NULL},
|
||||
{"fnorm.s.s0", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL},
|
||||
{"fnorm.s", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL},
|
||||
{"fnorm.s.s1", f, OpXaSfF2F4 (0x8, 1, 1, 0, 1), {F1, F3}, PSEUDO, 0, NULL},
|
||||
{"fnorm.s.s2", f, OpXaSfF2F4 (0x8, 1, 2, 0, 1), {F1, F3}, PSEUDO, 0, NULL},
|
||||
{"fnorm.s.s3", f, OpXaSfF2F4 (0x8, 1, 3, 0, 1), {F1, F3}, PSEUDO, 0, NULL},
|
||||
{"fcvt.xuf.s0", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL},
|
||||
{"fcvt.xuf", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL},
|
||||
{"fcvt.xuf.s1", f, OpXaSfF2F4 (0x8, 0, 1, 0, 1), {F1, F3}, PSEUDO, 0, NULL},
|
||||
{"fcvt.xuf.s2", f, OpXaSfF2F4 (0x8, 0, 2, 0, 1), {F1, F3}, PSEUDO, 0, NULL},
|
||||
{"fcvt.xuf.s3", f, OpXaSfF2F4 (0x8, 0, 3, 0, 1), {F1, F3}, PSEUDO, 0, NULL},
|
||||
{"fcvt.xuf.s.s0", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL},
|
||||
{"fcvt.xuf.s", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL},
|
||||
{"fcvt.xuf.s.s1", f, OpXaSfF2F4 (0x8, 1, 1, 0, 1), {F1, F3}, PSEUDO, 0, NULL},
|
||||
{"fcvt.xuf.s.s2", f, OpXaSfF2F4 (0x8, 1, 2, 0, 1), {F1, F3}, PSEUDO, 0, NULL},
|
||||
{"fcvt.xuf.s.s3", f, OpXaSfF2F4 (0x8, 1, 3, 0, 1), {F1, F3}, PSEUDO, 0, NULL},
|
||||
{"fadd.s0", f, OpXaSfF4 (0x8, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fadd", f, OpXaSfF4 (0x8, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fadd.s1", f, OpXaSfF4 (0x8, 0, 1, 1), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fadd.s2", f, OpXaSfF4 (0x8, 0, 2, 1), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fadd.s3", f, OpXaSfF4 (0x8, 0, 3, 1), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fadd.s.s0", f, OpXaSfF4 (0x8, 1, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fadd.s", f, OpXaSfF4 (0x8, 1, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fadd.s.s1", f, OpXaSfF4 (0x8, 1, 1, 1), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fadd.s.s2", f, OpXaSfF4 (0x8, 1, 2, 1), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fadd.s.s3", f, OpXaSfF4 (0x8, 1, 3, 1), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fmpy.s0", f, OpXaSfF2 (0x8, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"fmpy", f, OpXaSfF2 (0x8, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"fmpy.s1", f, OpXaSfF2 (0x8, 0, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"fmpy.s2", f, OpXaSfF2 (0x8, 0, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"fmpy.s3", f, OpXaSfF2 (0x8, 0, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"fmpy.s.s0", f, OpXaSfF2 (0x8, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"fmpy.s", f, OpXaSfF2 (0x8, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"fmpy.s.s1", f, OpXaSfF2 (0x8, 1, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"fmpy.s.s2", f, OpXaSfF2 (0x8, 1, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"fmpy.s.s3", f, OpXaSfF2 (0x8, 1, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"fma.s0", f, OpXaSf (0x8, 0, 0), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fma", f, OpXaSf (0x8, 0, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL},
|
||||
{"fma.s1", f, OpXaSf (0x8, 0, 1), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fma.s2", f, OpXaSf (0x8, 0, 2), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fma.s3", f, OpXaSf (0x8, 0, 3), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fma.s.s0", f, OpXaSf (0x8, 1, 0), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fma.s", f, OpXaSf (0x8, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL},
|
||||
{"fma.s.s1", f, OpXaSf (0x8, 1, 1), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fma.s.s2", f, OpXaSf (0x8, 1, 2), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fma.s.s3", f, OpXaSf (0x8, 1, 3), {F1, F3, F4, F2}, EMPTY},
|
||||
|
||||
{"fnorm.d.s0", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL},
|
||||
{"fnorm.d", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL},
|
||||
{"fnorm.d.s1", f, OpXaSfF2F4 (0x9, 0, 1, 0, 1), {F1, F3}, PSEUDO, 0, NULL},
|
||||
{"fnorm.d.s2", f, OpXaSfF2F4 (0x9, 0, 2, 0, 1), {F1, F3}, PSEUDO, 0, NULL},
|
||||
{"fnorm.d.s3", f, OpXaSfF2F4 (0x9, 0, 3, 0, 1), {F1, F3}, PSEUDO, 0, NULL},
|
||||
{"fcvt.xuf.d.s0", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL},
|
||||
{"fcvt.xuf.d", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL},
|
||||
{"fcvt.xuf.d.s1", f, OpXaSfF2F4 (0x9, 0, 1, 0, 1), {F1, F3}, PSEUDO, 0, NULL},
|
||||
{"fcvt.xuf.d.s2", f, OpXaSfF2F4 (0x9, 0, 2, 0, 1), {F1, F3}, PSEUDO, 0, NULL},
|
||||
{"fcvt.xuf.d.s3", f, OpXaSfF2F4 (0x9, 0, 3, 0, 1), {F1, F3}, PSEUDO, 0, NULL},
|
||||
{"fadd.d.s0", f, OpXaSfF4 (0x9, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fadd.d", f, OpXaSfF4 (0x9, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fadd.d.s1", f, OpXaSfF4 (0x9, 0, 1, 1), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fadd.d.s2", f, OpXaSfF4 (0x9, 0, 2, 1), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fadd.d.s3", f, OpXaSfF4 (0x9, 0, 3, 1), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fmpy.d.s0", f, OpXaSfF2 (0x9, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"fmpy.d", f, OpXaSfF2 (0x9, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"fmpy.d.s1", f, OpXaSfF2 (0x9, 0, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"fmpy.d.s2", f, OpXaSfF2 (0x9, 0, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"fmpy.d.s3", f, OpXaSfF2 (0x9, 0, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"fma.d.s0", f, OpXaSf (0x9, 0, 0), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fma.d", f, OpXaSf (0x9, 0, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL},
|
||||
{"fma.d.s1", f, OpXaSf (0x9, 0, 1), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fma.d.s2", f, OpXaSf (0x9, 0, 2), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fma.d.s3", f, OpXaSf (0x9, 0, 3), {F1, F3, F4, F2}, EMPTY},
|
||||
|
||||
{"fpmpy.s0", f, OpXaSfF2 (0x9, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"fpmpy", f, OpXaSfF2 (0x9, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"fpmpy.s1", f, OpXaSfF2 (0x9, 1, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"fpmpy.s2", f, OpXaSfF2 (0x9, 1, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"fpmpy.s3", f, OpXaSfF2 (0x9, 1, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"fpma.s0", f, OpXaSf (0x9, 1, 0), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fpma", f, OpXaSf (0x9, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL},
|
||||
{"fpma.s1", f, OpXaSf (0x9, 1, 1), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fpma.s2", f, OpXaSf (0x9, 1, 2), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fpma.s3", f, OpXaSf (0x9, 1, 3), {F1, F3, F4, F2}, EMPTY},
|
||||
|
||||
{"fsub.s0", f, OpXaSfF4 (0xa, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fsub", f, OpXaSfF4 (0xa, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fsub.s1", f, OpXaSfF4 (0xa, 0, 1, 1), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fsub.s2", f, OpXaSfF4 (0xa, 0, 2, 1), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fsub.s3", f, OpXaSfF4 (0xa, 0, 3, 1), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fsub.s.s0", f, OpXaSfF4 (0xa, 1, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fsub.s", f, OpXaSfF4 (0xa, 1, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fsub.s.s1", f, OpXaSfF4 (0xa, 1, 1, 1), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fsub.s.s2", f, OpXaSfF4 (0xa, 1, 2, 1), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fsub.s.s3", f, OpXaSfF4 (0xa, 1, 3, 1), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fms.s0", f, OpXaSf (0xa, 0, 0), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fms", f, OpXaSf (0xa, 0, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL},
|
||||
{"fms.s1", f, OpXaSf (0xa, 0, 1), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fms.s2", f, OpXaSf (0xa, 0, 2), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fms.s3", f, OpXaSf (0xa, 0, 3), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fms.s.s0", f, OpXaSf (0xa, 1, 0), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fms.s", f, OpXaSf (0xa, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL},
|
||||
{"fms.s.s1", f, OpXaSf (0xa, 1, 1), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fms.s.s2", f, OpXaSf (0xa, 1, 2), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fms.s.s3", f, OpXaSf (0xa, 1, 3), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fsub.d.s0", f, OpXaSfF4 (0xb, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fsub.d", f, OpXaSfF4 (0xb, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fsub.d.s1", f, OpXaSfF4 (0xb, 0, 1, 1), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fsub.d.s2", f, OpXaSfF4 (0xb, 0, 2, 1), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fsub.d.s3", f, OpXaSfF4 (0xb, 0, 3, 1), {F1, F3, F2}, PSEUDO, 0, NULL},
|
||||
{"fms.d.s0", f, OpXaSf (0xb, 0, 0), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fms.d", f, OpXaSf (0xb, 0, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL},
|
||||
{"fms.d.s1", f, OpXaSf (0xb, 0, 1), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fms.d.s2", f, OpXaSf (0xb, 0, 2), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fms.d.s3", f, OpXaSf (0xb, 0, 3), {F1, F3, F4, F2}, EMPTY},
|
||||
|
||||
{"fpms.s0", f, OpXaSf (0xb, 1, 0), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fpms", f, OpXaSf (0xb, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL},
|
||||
{"fpms.s1", f, OpXaSf (0xb, 1, 1), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fpms.s2", f, OpXaSf (0xb, 1, 2), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fpms.s3", f, OpXaSf (0xb, 1, 3), {F1, F3, F4, F2}, EMPTY},
|
||||
|
||||
{"fnmpy.s0", f, OpXaSfF2 (0xc, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"fnmpy", f, OpXaSfF2 (0xc, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"fnmpy.s1", f, OpXaSfF2 (0xc, 0, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"fnmpy.s2", f, OpXaSfF2 (0xc, 0, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"fnmpy.s3", f, OpXaSfF2 (0xc, 0, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"fnmpy.s.s0", f, OpXaSfF2 (0xc, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"fnmpy.s", f, OpXaSfF2 (0xc, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"fnmpy.s.s1", f, OpXaSfF2 (0xc, 1, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"fnmpy.s.s2", f, OpXaSfF2 (0xc, 1, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"fnmpy.s.s3", f, OpXaSfF2 (0xc, 1, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"fnma.s0", f, OpXaSf (0xc, 0, 0), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fnma", f, OpXaSf (0xc, 0, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL},
|
||||
{"fnma.s1", f, OpXaSf (0xc, 0, 1), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fnma.s2", f, OpXaSf (0xc, 0, 2), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fnma.s3", f, OpXaSf (0xc, 0, 3), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fnma.s.s0", f, OpXaSf (0xc, 1, 0), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fnma.s", f, OpXaSf (0xc, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL},
|
||||
{"fnma.s.s1", f, OpXaSf (0xc, 1, 1), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fnma.s.s2", f, OpXaSf (0xc, 1, 2), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fnma.s.s3", f, OpXaSf (0xc, 1, 3), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fnmpy.d.s0", f, OpXaSfF2 (0xd, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"fnmpy.d", f, OpXaSfF2 (0xd, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"fnmpy.d.s1", f, OpXaSfF2 (0xd, 0, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"fnmpy.d.s2", f, OpXaSfF2 (0xd, 0, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"fnmpy.d.s3", f, OpXaSfF2 (0xd, 0, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"fnma.d.s0", f, OpXaSf (0xd, 0, 0), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fnma.d", f, OpXaSf (0xd, 0, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL},
|
||||
{"fnma.d.s1", f, OpXaSf (0xd, 0, 1), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fnma.d.s2", f, OpXaSf (0xd, 0, 2), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fnma.d.s3", f, OpXaSf (0xd, 0, 3), {F1, F3, F4, F2}, EMPTY},
|
||||
|
||||
{"fpnmpy.s0", f, OpXaSfF2 (0xd, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"fpnmpy", f, OpXaSfF2 (0xd, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"fpnmpy.s1", f, OpXaSfF2 (0xd, 1, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"fpnmpy.s2", f, OpXaSfF2 (0xd, 1, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"fpnmpy.s3", f, OpXaSfF2 (0xd, 1, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"fpnma.s0", f, OpXaSf (0xd, 1, 0), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fpnma", f, OpXaSf (0xd, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL},
|
||||
{"fpnma.s1", f, OpXaSf (0xd, 1, 1), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fpnma.s2", f, OpXaSf (0xd, 1, 2), {F1, F3, F4, F2}, EMPTY},
|
||||
{"fpnma.s3", f, OpXaSf (0xd, 1, 3), {F1, F3, F4, F2}, EMPTY},
|
||||
|
||||
{"xmpy.l", f, OpXaX2F2 (0xe, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"xmpy.lu", f, OpXaX2F2 (0xe, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"xmpy.h", f, OpXaX2F2 (0xe, 1, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"xmpy.hu", f, OpXaX2F2 (0xe, 1, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL},
|
||||
{"xma.l", f, OpXaX2 (0xe, 1, 0), {F1, F3, F4, F2}, EMPTY},
|
||||
{"xma.lu", f, OpXaX2 (0xe, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL},
|
||||
{"xma.h", f, OpXaX2 (0xe, 1, 3), {F1, F3, F4, F2}, EMPTY},
|
||||
{"xma.hu", f, OpXaX2 (0xe, 1, 2), {F1, F3, F4, F2}, EMPTY},
|
||||
|
||||
{"fselect", f, OpXa (0xe, 0), {F1, F3, F4, F2}, EMPTY},
|
||||
|
||||
{NULL, 0, 0, 0, 0, {0}, 0, 0, NULL}
|
||||
};
|
||||
|
||||
#undef f0
|
||||
#undef f
|
||||
#undef f2
|
||||
#undef bF2
|
||||
#undef bF4
|
||||
#undef bQ
|
||||
#undef bRa
|
||||
#undef bRb
|
||||
#undef bSf
|
||||
#undef bTa
|
||||
#undef bXa
|
||||
#undef bXb
|
||||
#undef bX2
|
||||
#undef bX6
|
||||
#undef mF2
|
||||
#undef mF4
|
||||
#undef mQ
|
||||
#undef mRa
|
||||
#undef mRb
|
||||
#undef mSf
|
||||
#undef mTa
|
||||
#undef mXa
|
||||
#undef mXb
|
||||
#undef mX2
|
||||
#undef mX6
|
||||
#undef OpXa
|
||||
#undef OpXaSf
|
||||
#undef OpXaSfF2
|
||||
#undef OpXaSfF4
|
||||
#undef OpXaSfF2F4
|
||||
#undef OpXaX2
|
||||
#undef OpRaRbTaSf
|
||||
#undef OpTa
|
||||
#undef OpXbQSf
|
||||
#undef OpXbX6
|
||||
#undef OpXbX6F2
|
||||
#undef OpXbX6Sf
|
||||
#undef EMPTY
|
||||
@@ -1,338 +0,0 @@
|
||||
/* ia64-opc-i.c -- IA-64 `I' opcode table.
|
||||
Copyright 1998, 1999, 2000, 2002, 2005, 2006
|
||||
Free Software Foundation, Inc.
|
||||
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
|
||||
|
||||
This file is part of GDB, GAS, and the GNU binutils.
|
||||
|
||||
GDB, GAS, and the GNU binutils are free software; you can redistribute
|
||||
them and/or modify them under the terms of the GNU General Public
|
||||
License as published by the Free Software Foundation; either version
|
||||
2, or (at your option) any later version.
|
||||
|
||||
GDB, GAS, and the GNU binutils are distributed in the hope that they
|
||||
will be useful, but WITHOUT ANY WARRANTY; without even the implied
|
||||
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
|
||||
the GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this file; see the file COPYING. If not, write to the
|
||||
Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
|
||||
02110-1301, USA. */
|
||||
|
||||
#include "ia64-opc.h"
|
||||
|
||||
#define I0 IA64_TYPE_I, 0
|
||||
#define I IA64_TYPE_I, 1
|
||||
#define I2 IA64_TYPE_I, 2
|
||||
|
||||
/* instruction bit fields: */
|
||||
#define bC(x) (((ia64_insn) ((x) & 0x1)) << 12)
|
||||
#define bIh(x) (((ia64_insn) ((x) & 0x1)) << 23)
|
||||
#define bTa(x) (((ia64_insn) ((x) & 0x1)) << 33)
|
||||
#define bTag13(x) (((ia64_insn) ((x) & 0x1)) << 33)
|
||||
#define bTb(x) (((ia64_insn) ((x) & 0x1)) << 36)
|
||||
#define bVc(x) (((ia64_insn) ((x) & 0x1)) << 20)
|
||||
#define bVe(x) (((ia64_insn) ((x) & 0x1)) << 32)
|
||||
#define bWh(x) (((ia64_insn) ((x) & 0x3)) << 20)
|
||||
#define bX(x) (((ia64_insn) ((x) & 0x1)) << 33)
|
||||
#define bXb(x) (((ia64_insn) ((x) & 0x1)) << 22)
|
||||
#define bXc(x) (((ia64_insn) ((x) & 0x1)) << 19)
|
||||
#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 34)
|
||||
#define bX2a(x) (((ia64_insn) ((x) & 0x3)) << 34)
|
||||
#define bX2b(x) (((ia64_insn) ((x) & 0x3)) << 28)
|
||||
#define bX2c(x) (((ia64_insn) ((x) & 0x3)) << 30)
|
||||
#define bX3(x) (((ia64_insn) ((x) & 0x7)) << 33)
|
||||
#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27)
|
||||
#define bYa(x) (((ia64_insn) ((x) & 0x1)) << 13)
|
||||
#define bYb(x) (((ia64_insn) ((x) & 0x1)) << 26)
|
||||
#define bZa(x) (((ia64_insn) ((x) & 0x1)) << 36)
|
||||
#define bZb(x) (((ia64_insn) ((x) & 0x1)) << 33)
|
||||
|
||||
/* instruction bit masks: */
|
||||
#define mC bC (-1)
|
||||
#define mIh bIh (-1)
|
||||
#define mTa bTa (-1)
|
||||
#define mTag13 bTag13 (-1)
|
||||
#define mTb bTb (-1)
|
||||
#define mVc bVc (-1)
|
||||
#define mVe bVe (-1)
|
||||
#define mWh bWh (-1)
|
||||
#define mX bX (-1)
|
||||
#define mXb bXb (-1)
|
||||
#define mXc bXc (-1)
|
||||
#define mX2 bX2 (-1)
|
||||
#define mX2a bX2a (-1)
|
||||
#define mX2b bX2b (-1)
|
||||
#define mX2c bX2c (-1)
|
||||
#define mX3 bX3 (-1)
|
||||
#define mX6 bX6 (-1)
|
||||
#define mYa bYa (-1)
|
||||
#define mYb bYb (-1)
|
||||
#define mZa bZa (-1)
|
||||
#define mZb bZb (-1)
|
||||
|
||||
#define OpZaZbVeX2aX2b(a,b,c,d,e,f) \
|
||||
(bOp (a) | bZa (b) | bZb (c) | bVe (d) | bX2a (e) | bX2b (f)), \
|
||||
(mOp | mZa | mZb | mVe | mX2a | mX2b)
|
||||
#define OpZaZbVeX2aX2bX2c(a,b,c,d,e,f,g) \
|
||||
(bOp (a) | bZa (b) | bZb (c) | bVe (d) | bX2a (e) | bX2b (f) | bX2c (g)), \
|
||||
(mOp | mZa | mZb | mVe | mX2a | mX2b | mX2c)
|
||||
#define OpX2X(a,b,c) (bOp (a) | bX2 (b) | bX (c)), (mOp | mX2 | mX)
|
||||
#define OpX2XYa(a,b,c,d) (bOp (a) | bX2 (b) | bX (c) | bYa (d)), \
|
||||
(mOp | mX2 | mX | mYa)
|
||||
#define OpX2XYb(a,b,c,d) (bOp (a) | bX2 (b) | bX (c) | bYb (d)), \
|
||||
(mOp | mX2 | mX | mYb)
|
||||
#define OpX2TaTbYaC(a,b,c,d,e,f) \
|
||||
(bOp (a) | bX2 (b) | bTa (c) | bTb (d) | bYa (e) | bC (f)), \
|
||||
(mOp | mX2 | mTa | mTb | mYa | mC)
|
||||
#define OpX2TaTbYaXcC(a,b,c,d,e,f,g) \
|
||||
(bOp (a) | bX2 (b) | bTa (c) | bTb (d) | bYa (e) | bXc (f) | bC (g)), \
|
||||
(mOp | mX2 | mTa | mTb | mYa | mXc | mC)
|
||||
#define OpX3(a,b) (bOp (a) | bX3 (b)), (mOp | mX3)
|
||||
#define OpX3X6(a,b,c) (bOp (a) | bX3 (b) | bX6(c)), \
|
||||
(mOp | mX3 | mX6)
|
||||
#define OpX3X6Yb(a,b,c,d) (bOp (a) | bX3 (b) | bX6(c) | bYb(d)), \
|
||||
(mOp | mX3 | mX6 | mYb)
|
||||
#define OpX3XbIhWh(a,b,c,d,e) \
|
||||
(bOp (a) | bX3 (b) | bXb (c) | bIh (d) | bWh (e)), \
|
||||
(mOp | mX3 | mXb | mIh | mWh)
|
||||
#define OpX3XbIhWhTag13(a,b,c,d,e,f) \
|
||||
(bOp (a) | bX3 (b) | bXb (c) | bIh (d) | bWh (e) | bTag13 (f)), \
|
||||
(mOp | mX3 | mXb | mIh | mWh | mTag13)
|
||||
|
||||
#define FULL17 ((ia64_insn)0x10ff001fc0LL)
|
||||
|
||||
/* Used to initialise unused fields in ia64_opcode struct,
|
||||
in order to stop gcc from complaining. */
|
||||
#define EMPTY 0,0,NULL
|
||||
|
||||
struct ia64_opcode ia64_opcodes_i[] =
|
||||
{
|
||||
/* I-type instruction encodings (sorted according to major opcode). */
|
||||
|
||||
{"break.i", I0, OpX3X6 (0, 0, 0x00), {IMMU21}, X_IN_MLX, 0, NULL},
|
||||
{"nop.i", I0, OpX3X6Yb (0, 0, 0x01, 0), {IMMU21}, X_IN_MLX, 0, NULL},
|
||||
{"hint.i", I0, OpX3X6Yb (0, 0, 0x01, 1), {IMMU21}, X_IN_MLX, 0, NULL},
|
||||
{"chk.s.i", I0, OpX3 (0, 1), {R2, TGT25b}, EMPTY},
|
||||
|
||||
{"mov", I, OpX3XbIhWhTag13 (0, 7, 0, 0, 1, 0), {B1, R2}, PSEUDO, 0, NULL},
|
||||
#define MOV(a,b,c,d) \
|
||||
I, OpX3XbIhWh (0, a, b, c, d), {B1, R2, TAG13b}, EMPTY
|
||||
{"mov.sptk", MOV (7, 0, 0, 0)},
|
||||
{"mov.sptk.imp", MOV (7, 0, 1, 0)},
|
||||
{"mov", MOV (7, 0, 0, 1)},
|
||||
{"mov.imp", MOV (7, 0, 1, 1)},
|
||||
{"mov.dptk", MOV (7, 0, 0, 2)},
|
||||
{"mov.dptk.imp", MOV (7, 0, 1, 2)},
|
||||
{"mov.ret.sptk", MOV (7, 1, 0, 0)},
|
||||
{"mov.ret.sptk.imp", MOV (7, 1, 1, 0)},
|
||||
{"mov.ret", MOV (7, 1, 0, 1)},
|
||||
{"mov.ret.imp", MOV (7, 1, 1, 1)},
|
||||
{"mov.ret.dptk", MOV (7, 1, 0, 2)},
|
||||
{"mov.ret.dptk.imp", MOV (7, 1, 1, 2)},
|
||||
#undef MOV
|
||||
{"mov", I, OpX3X6 (0, 0, 0x31), {R1, B2}, EMPTY},
|
||||
{"mov", I, OpX3 (0, 3), {PR, R2, IMM17}, EMPTY},
|
||||
/* Don't remove one of the seemingly redundant FULL17-s. */
|
||||
{"mov", I, FULL17 | OpX3 (0, 3) | FULL17, {PR, R2}, PSEUDO, 0, NULL},
|
||||
{"mov", I, OpX3 (0, 2), {PR_ROT, IMM44}, EMPTY},
|
||||
{"mov", I, OpX3X6 (0, 0, 0x30), {R1, IP}, EMPTY},
|
||||
{"mov", I, OpX3X6 (0, 0, 0x33), {R1, PR}, EMPTY},
|
||||
{"mov.i", I, OpX3X6 (0, 0, 0x2a), {AR3, R2}, EMPTY},
|
||||
{"mov.i", I, OpX3X6 (0, 0, 0x0a), {AR3, IMM8}, EMPTY},
|
||||
{"mov.i", I, OpX3X6 (0, 0, 0x32), {R1, AR3}, EMPTY},
|
||||
{"zxt1", I, OpX3X6 (0, 0, 0x10), {R1, R3}, EMPTY},
|
||||
{"zxt2", I, OpX3X6 (0, 0, 0x11), {R1, R3}, EMPTY},
|
||||
{"zxt4", I, OpX3X6 (0, 0, 0x12), {R1, R3}, EMPTY},
|
||||
{"sxt1", I, OpX3X6 (0, 0, 0x14), {R1, R3}, EMPTY},
|
||||
{"sxt2", I, OpX3X6 (0, 0, 0x15), {R1, R3}, EMPTY},
|
||||
{"sxt4", I, OpX3X6 (0, 0, 0x16), {R1, R3}, EMPTY},
|
||||
{"czx1.l", I, OpX3X6 (0, 0, 0x18), {R1, R3}, EMPTY},
|
||||
{"czx2.l", I, OpX3X6 (0, 0, 0x19), {R1, R3}, EMPTY},
|
||||
{"czx1.r", I, OpX3X6 (0, 0, 0x1c), {R1, R3}, EMPTY},
|
||||
{"czx2.r", I, OpX3X6 (0, 0, 0x1d), {R1, R3}, EMPTY},
|
||||
|
||||
{"dep", I, Op (4), {R1, R2, R3, CPOS6c, LEN4}, EMPTY},
|
||||
|
||||
{"shrp", I, OpX2X (5, 3, 0), {R1, R2, R3, CNT6}, EMPTY},
|
||||
|
||||
{"shr.u", I, OpX2XYa (5, 1, 0, 0), {R1, R3, POS6},
|
||||
PSEUDO | LEN_EQ_64MCNT, 0, NULL},
|
||||
{"extr.u", I, OpX2XYa (5, 1, 0, 0), {R1, R3, POS6, LEN6}, EMPTY},
|
||||
|
||||
{"shr", I, OpX2XYa (5, 1, 0, 1), {R1, R3, POS6},
|
||||
PSEUDO | LEN_EQ_64MCNT, 0, NULL},
|
||||
{"extr", I, OpX2XYa (5, 1, 0, 1), {R1, R3, POS6, LEN6}, EMPTY},
|
||||
|
||||
{"shl", I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a},
|
||||
PSEUDO | LEN_EQ_64MCNT, 0, NULL},
|
||||
{"dep.z", I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a, LEN6}, EMPTY},
|
||||
{"dep.z", I, OpX2XYb (5, 1, 1, 1), {R1, IMM8, CPOS6a, LEN6}, EMPTY},
|
||||
{"dep", I, OpX2X (5, 3, 1), {R1, IMM1, R3, CPOS6b, LEN6}, EMPTY},
|
||||
#define TF(a,b,c) \
|
||||
I2, OpX2TaTbYaXcC (5, 0, a, b, 1, 1, c), {P1, P2, IMMU5b}, EMPTY
|
||||
#define TFCM(a,b,c) \
|
||||
I2, OpX2TaTbYaXcC (5, 0, a, b, 1, 1, c), {P2, P1, IMMU5b}, PSEUDO, 0, NULL
|
||||
{"tf.z", TF (0, 0, 0)},
|
||||
{"tf.nz", TFCM (0, 0, 0)},
|
||||
{"tf.z.unc", TF (0, 0, 1)},
|
||||
{"tf.nz.unc", TFCM (0, 0, 1)},
|
||||
{"tf.z.and", TF (0, 1, 0)},
|
||||
{"tf.nz.andcm", TFCM (0, 1, 0)},
|
||||
{"tf.nz.and", TF (0, 1, 1)},
|
||||
{"tf.z.andcm", TFCM (0, 1, 1)},
|
||||
{"tf.z.or", TF (1, 0, 0)},
|
||||
{"tf.nz.orcm", TFCM (1, 0, 0)},
|
||||
{"tf.nz.or", TF (1, 0, 1)},
|
||||
{"tf.z.orcm", TFCM (1, 0, 1)},
|
||||
{"tf.z.or.andcm", TF (1, 1, 0)},
|
||||
{"tf.nz.and.orcm", TFCM (1, 1, 0)},
|
||||
{"tf.nz.or.andcm", TF (1, 1, 1)},
|
||||
{"tf.z.and.orcm", TFCM (1, 1, 1)},
|
||||
#undef TF
|
||||
#undef TFCM
|
||||
#define TBIT(a,b,c,d) \
|
||||
I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3, POS6}, EMPTY
|
||||
#define TBITCM(a,b,c,d) \
|
||||
I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P2, P1, R3, POS6}, PSEUDO, 0, NULL
|
||||
{"tbit.z", TBIT (0, 0, 0, 0)},
|
||||
{"tbit.nz", TBITCM (0, 0, 0, 0)},
|
||||
{"tbit.z.unc", TBIT (0, 0, 0, 1)},
|
||||
{"tbit.nz.unc", TBITCM (0, 0, 0, 1)},
|
||||
{"tbit.z.and", TBIT (0, 1, 0, 0)},
|
||||
{"tbit.nz.andcm", TBITCM (0, 1, 0, 0)},
|
||||
{"tbit.nz.and", TBIT (0, 1, 0, 1)},
|
||||
{"tbit.z.andcm", TBITCM (0, 1, 0, 1)},
|
||||
{"tbit.z.or", TBIT (1, 0, 0, 0)},
|
||||
{"tbit.nz.orcm", TBITCM (1, 0, 0, 0)},
|
||||
{"tbit.nz.or", TBIT (1, 0, 0, 1)},
|
||||
{"tbit.z.orcm", TBITCM (1, 0, 0, 1)},
|
||||
{"tbit.z.or.andcm", TBIT (1, 1, 0, 0)},
|
||||
{"tbit.nz.and.orcm", TBITCM (1, 1, 0, 0)},
|
||||
{"tbit.nz.or.andcm", TBIT (1, 1, 0, 1)},
|
||||
{"tbit.z.and.orcm", TBITCM (1, 1, 0, 1)},
|
||||
#undef TBIT
|
||||
#undef TBITCM
|
||||
#define TNAT(a,b,c,d) \
|
||||
I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3}, EMPTY
|
||||
#define TNATCM(a,b,c,d) \
|
||||
I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P2, P1, R3}, PSEUDO, 0, NULL
|
||||
{"tnat.z", TNAT (0, 0, 1, 0)},
|
||||
{"tnat.nz", TNATCM (0, 0, 1, 0)},
|
||||
{"tnat.z.unc", TNAT (0, 0, 1, 1)},
|
||||
{"tnat.nz.unc", TNATCM (0, 0, 1, 1)},
|
||||
{"tnat.z.and", TNAT (0, 1, 1, 0)},
|
||||
{"tnat.nz.andcm", TNATCM (0, 1, 1, 0)},
|
||||
{"tnat.nz.and", TNAT (0, 1, 1, 1)},
|
||||
{"tnat.z.andcm", TNATCM (0, 1, 1, 1)},
|
||||
{"tnat.z.or", TNAT (1, 0, 1, 0)},
|
||||
{"tnat.nz.orcm", TNATCM (1, 0, 1, 0)},
|
||||
{"tnat.nz.or", TNAT (1, 0, 1, 1)},
|
||||
{"tnat.z.orcm", TNATCM (1, 0, 1, 1)},
|
||||
{"tnat.z.or.andcm", TNAT (1, 1, 1, 0)},
|
||||
{"tnat.nz.and.orcm", TNATCM (1, 1, 1, 0)},
|
||||
{"tnat.nz.or.andcm", TNAT (1, 1, 1, 1)},
|
||||
{"tnat.z.and.orcm", TNATCM (1, 1, 1, 1)},
|
||||
#undef TNAT
|
||||
#undef TNATCM
|
||||
|
||||
{"pmpyshr2", I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 3), {R1, R2, R3, CNT2c}, EMPTY},
|
||||
{"pmpyshr2.u", I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 1), {R1, R2, R3, CNT2c}, EMPTY},
|
||||
{"pmpy2.r", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 1, 3), {R1, R2, R3}, EMPTY},
|
||||
{"pmpy2.l", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 3), {R1, R2, R3}, EMPTY},
|
||||
{"mix1.r", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 0, 2), {R1, R2, R3}, EMPTY},
|
||||
{"mix2.r", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 2), {R1, R2, R3}, EMPTY},
|
||||
{"mix4.r", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 0, 2), {R1, R2, R3}, EMPTY},
|
||||
{"mix1.l", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 2, 2), {R1, R2, R3}, EMPTY},
|
||||
{"mix2.l", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 2), {R1, R2, R3}, EMPTY},
|
||||
{"mix4.l", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 2), {R1, R2, R3}, EMPTY},
|
||||
{"pack2.uss", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 0), {R1, R2, R3}, EMPTY},
|
||||
{"pack2.sss", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 0), {R1, R2, R3}, EMPTY},
|
||||
{"pack4.sss", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 0), {R1, R2, R3}, EMPTY},
|
||||
{"unpack1.h", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 0, 1), {R1, R2, R3}, EMPTY},
|
||||
{"unpack2.h", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 1), {R1, R2, R3}, EMPTY},
|
||||
{"unpack4.h", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 0, 1), {R1, R2, R3}, EMPTY},
|
||||
{"unpack1.l", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 2, 1), {R1, R2, R3}, EMPTY},
|
||||
{"unpack2.l", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 1), {R1, R2, R3}, EMPTY},
|
||||
{"unpack4.l", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 1), {R1, R2, R3}, EMPTY},
|
||||
{"pmin1.u", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 1, 0), {R1, R2, R3}, EMPTY},
|
||||
{"pmax1.u", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 1, 1), {R1, R2, R3}, EMPTY},
|
||||
{"pmin2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 0), {R1, R2, R3}, EMPTY},
|
||||
{"pmax2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 1), {R1, R2, R3}, EMPTY},
|
||||
{"psad1", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 3, 2), {R1, R2, R3}, EMPTY},
|
||||
{"mux1", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 3, 2, 2), {R1, R2, MBTYPE4}, EMPTY},
|
||||
{"mux2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 3, 2, 2), {R1, R2, MHTYPE8}, EMPTY},
|
||||
{"pshr2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 2, 0), {R1, R3, R2}, EMPTY},
|
||||
{"pshr4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 2, 0), {R1, R3, R2}, EMPTY},
|
||||
{"shr", I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 2, 0), {R1, R3, R2}, EMPTY},
|
||||
{"pshr2.u", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 0, 0), {R1, R3, R2}, EMPTY},
|
||||
{"pshr4.u", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 0, 0), {R1, R3, R2}, EMPTY},
|
||||
{"shr.u", I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 0, 0), {R1, R3, R2}, EMPTY},
|
||||
{"pshr2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 3, 0), {R1, R3, CNT5}, EMPTY},
|
||||
{"pshr4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 1, 3, 0), {R1, R3, CNT5}, EMPTY},
|
||||
{"pshr2.u", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 0), {R1, R3, CNT5}, EMPTY},
|
||||
{"pshr4.u", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 1, 1, 0), {R1, R3, CNT5}, EMPTY},
|
||||
{"pshl2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 0, 1), {R1, R2, R3}, EMPTY},
|
||||
{"pshl4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 0, 1), {R1, R2, R3}, EMPTY},
|
||||
{"shl", I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 0, 1), {R1, R2, R3}, EMPTY},
|
||||
{"pshl2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 3, 1, 1), {R1, R2, CCNT5}, EMPTY},
|
||||
{"pshl4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 3, 1, 1), {R1, R2, CCNT5}, EMPTY},
|
||||
{"popcnt", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 2), {R1, R3}, EMPTY},
|
||||
|
||||
{NULL, 0, 0, 0, 0, {0}, 0, 0, NULL}
|
||||
};
|
||||
|
||||
#undef I0
|
||||
#undef I
|
||||
#undef I2
|
||||
#undef L
|
||||
#undef bC
|
||||
#undef bIh
|
||||
#undef bTa
|
||||
#undef bTag13
|
||||
#undef bTb
|
||||
#undef bVc
|
||||
#undef bVe
|
||||
#undef bWh
|
||||
#undef bX
|
||||
#undef bXb
|
||||
#undef bX2
|
||||
#undef bX2a
|
||||
#undef bX2b
|
||||
#undef bX2c
|
||||
#undef bX3
|
||||
#undef bX6
|
||||
#undef bY
|
||||
#undef bZa
|
||||
#undef bZb
|
||||
#undef mC
|
||||
#undef mIh
|
||||
#undef mTa
|
||||
#undef mTag13
|
||||
#undef mTb
|
||||
#undef mVc
|
||||
#undef mVe
|
||||
#undef mWh
|
||||
#undef mX
|
||||
#undef mXb
|
||||
#undef mX2
|
||||
#undef mX2a
|
||||
#undef mX2b
|
||||
#undef mX2c
|
||||
#undef mX3
|
||||
#undef mX6
|
||||
#undef mY
|
||||
#undef mZa
|
||||
#undef mZb
|
||||
#undef OpZaZbVeX2aX2b
|
||||
#undef OpZaZbVeX2aX2bX2c
|
||||
#undef OpX2X
|
||||
#undef OpX2XYa
|
||||
#undef OpX2XYb
|
||||
#undef OpX2TaTbYaC
|
||||
#undef OpX3
|
||||
#undef OpX3X6
|
||||
#undef OpX3XbIhWh
|
||||
#undef OpX3XbIhWhTag13
|
||||
#undef EMPTY
|
||||
File diff suppressed because it is too large.
Load diff
@@ -1,188 +0,0 @@
|
||||
/* ia64-opc-x.c -- IA-64 `X' opcode table.
|
||||
Copyright 1998, 1999, 2000, 2002 Free Software Foundation, Inc.
|
||||
Contributed by Timothy Wall <twall@cygnus.com>
|
||||
|
||||
This file is part of GDB, GAS, and the GNU binutils.
|
||||
|
||||
GDB, GAS, and the GNU binutils are free software; you can redistribute
|
||||
them and/or modify them under the terms of the GNU General Public
|
||||
License as published by the Free Software Foundation; either version
|
||||
2, or (at your option) any later version.
|
||||
|
||||
GDB, GAS, and the GNU binutils are distributed in the hope that they
|
||||
will be useful, but WITHOUT ANY WARRANTY; without even the implied
|
||||
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
|
||||
the GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this file; see the file COPYING. If not, write to the
|
||||
Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
|
||||
02110-1301, USA. */
|
||||
|
||||
#include "ia64-opc.h"
|
||||
|
||||
/* Identify the specific X-unit type. */
|
||||
#define X0 IA64_TYPE_X, 0
|
||||
#define X IA64_TYPE_X, 1
|
||||
|
||||
/* Instruction bit fields: */
|
||||
#define bBtype(x) (((ia64_insn) ((x) & 0x7)) << 6)
|
||||
#define bD(x) (((ia64_insn) ((x) & 0x1)) << 35)
|
||||
#define bPa(x) (((ia64_insn) ((x) & 0x1)) << 12)
|
||||
#define bPr(x) (((ia64_insn) ((x) & 0x3f)) << 0)
|
||||
#define bVc(x) (((ia64_insn) ((x) & 0x1)) << 20)
|
||||
#define bWha(x) (((ia64_insn) ((x) & 0x3)) << 33)
|
||||
#define bX3(x) (((ia64_insn) ((x) & 0x7)) << 33)
|
||||
#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27)
|
||||
#define bY(x) (((ia64_insn) ((x) & 0x1)) << 26)
|
||||
|
||||
#define mBtype bBtype (-1)
|
||||
#define mD bD (-1)
|
||||
#define mPa bPa (-1)
|
||||
#define mPr bPr (-1)
|
||||
#define mVc bVc (-1)
|
||||
#define mWha bWha (-1)
|
||||
#define mX3 bX3 (-1)
|
||||
#define mX6 bX6 (-1)
|
||||
#define mY bY (-1)
|
||||
|
||||
#define OpX3X6(a,b,c) (bOp (a) | bX3 (b) | bX6(c)), \
|
||||
(mOp | mX3 | mX6)
|
||||
#define OpX3X6Y(a,b,c,d) (bOp (a) | bX3 (b) | bX6(c) | bY(d)), \
|
||||
(mOp | mX3 | mX6 | mY)
|
||||
#define OpVc(a,b) (bOp (a) | bVc (b)), (mOp | mVc)
|
||||
#define OpPaWhaD(a,b,c,d) \
|
||||
(bOp (a) | bPa (b) | bWha (c) | bD (d)), (mOp | mPa | mWha | mD)
|
||||
#define OpBtypePaWhaD(a,b,c,d,e) \
|
||||
(bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e)), \
|
||||
(mOp | mBtype | mPa | mWha | mD)
|
||||
#define OpBtypePaWhaDPr(a,b,c,d,e,f) \
|
||||
(bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e) | bPr (f)), \
|
||||
(mOp | mBtype | mPa | mWha | mD | mPr)
|
||||
|
||||
struct ia64_opcode ia64_opcodes_x[] =
|
||||
{
|
||||
{"break.x", X0, OpX3X6 (0, 0, 0x00), {IMMU62}, 0, 0, NULL},
|
||||
{"nop.x", X0, OpX3X6Y (0, 0, 0x01, 0), {IMMU62}, 0, 0, NULL},
|
||||
{"hint.x", X0, OpX3X6Y (0, 0, 0x01, 1), {IMMU62}, 0, 0, NULL},
|
||||
{"movl", X, OpVc (6, 0), {R1, IMMU64}, 0, 0, NULL},
|
||||
#define BRL(a,b) \
|
||||
X0, OpBtypePaWhaDPr (0xC, 0, a, 0, b, 0), {TGT64}, PSEUDO, 0, NULL
|
||||
{"brl.few", BRL (0, 0)},
|
||||
{"brl", BRL (0, 0)},
|
||||
{"brl.few.clr", BRL (0, 1)},
|
||||
{"brl.clr", BRL (0, 1)},
|
||||
{"brl.many", BRL (1, 0)},
|
||||
{"brl.many.clr", BRL (1, 1)},
|
||||
#undef BRL
|
||||
#define BRL(a,b,c) \
|
||||
X0, OpBtypePaWhaD (0xC, 0, a, b, c), {TGT64}, 0, 0, NULL
|
||||
#define BRLP(a,b,c) \
|
||||
X0, OpBtypePaWhaD (0xC, 0, a, b, c), {TGT64}, PSEUDO, 0, NULL
|
||||
{"brl.cond.sptk.few", BRL (0, 0, 0)},
|
||||
{"brl.cond.sptk", BRLP (0, 0, 0)},
|
||||
{"brl.cond.sptk.few.clr", BRL (0, 0, 1)},
|
||||
{"brl.cond.sptk.clr", BRLP (0, 0, 1)},
|
||||
{"brl.cond.spnt.few", BRL (0, 1, 0)},
|
||||
{"brl.cond.spnt", BRLP (0, 1, 0)},
|
||||
{"brl.cond.spnt.few.clr", BRL (0, 1, 1)},
|
||||
{"brl.cond.spnt.clr", BRLP (0, 1, 1)},
|
||||
{"brl.cond.dptk.few", BRL (0, 2, 0)},
|
||||
{"brl.cond.dptk", BRLP (0, 2, 0)},
|
||||
{"brl.cond.dptk.few.clr", BRL (0, 2, 1)},
|
||||
{"brl.cond.dptk.clr", BRLP (0, 2, 1)},
|
||||
{"brl.cond.dpnt.few", BRL (0, 3, 0)},
|
||||
{"brl.cond.dpnt", BRLP (0, 3, 0)},
|
||||
{"brl.cond.dpnt.few.clr", BRL (0, 3, 1)},
|
||||
{"brl.cond.dpnt.clr", BRLP (0, 3, 1)},
|
||||
{"brl.cond.sptk.many", BRL (1, 0, 0)},
|
||||
{"brl.cond.sptk.many.clr", BRL (1, 0, 1)},
|
||||
{"brl.cond.spnt.many", BRL (1, 1, 0)},
|
||||
{"brl.cond.spnt.many.clr", BRL (1, 1, 1)},
|
||||
{"brl.cond.dptk.many", BRL (1, 2, 0)},
|
||||
{"brl.cond.dptk.many.clr", BRL (1, 2, 1)},
|
||||
{"brl.cond.dpnt.many", BRL (1, 3, 0)},
|
||||
{"brl.cond.dpnt.many.clr", BRL (1, 3, 1)},
|
||||
{"brl.sptk.few", BRL (0, 0, 0)},
|
||||
{"brl.sptk", BRLP (0, 0, 0)},
|
||||
{"brl.sptk.few.clr", BRL (0, 0, 1)},
|
||||
{"brl.sptk.clr", BRLP (0, 0, 1)},
|
||||
{"brl.spnt.few", BRL (0, 1, 0)},
|
||||
{"brl.spnt", BRLP (0, 1, 0)},
|
||||
{"brl.spnt.few.clr", BRL (0, 1, 1)},
|
||||
{"brl.spnt.clr", BRLP (0, 1, 1)},
|
||||
{"brl.dptk.few", BRL (0, 2, 0)},
|
||||
{"brl.dptk", BRLP (0, 2, 0)},
|
||||
{"brl.dptk.few.clr", BRL (0, 2, 1)},
|
||||
{"brl.dptk.clr", BRLP (0, 2, 1)},
|
||||
{"brl.dpnt.few", BRL (0, 3, 0)},
|
||||
{"brl.dpnt", BRLP (0, 3, 0)},
|
||||
{"brl.dpnt.few.clr", BRL (0, 3, 1)},
|
||||
{"brl.dpnt.clr", BRLP (0, 3, 1)},
|
||||
{"brl.sptk.many", BRL (1, 0, 0)},
|
||||
{"brl.sptk.many.clr", BRL (1, 0, 1)},
|
||||
{"brl.spnt.many", BRL (1, 1, 0)},
|
||||
{"brl.spnt.many.clr", BRL (1, 1, 1)},
|
||||
{"brl.dptk.many", BRL (1, 2, 0)},
|
||||
{"brl.dptk.many.clr", BRL (1, 2, 1)},
|
||||
{"brl.dpnt.many", BRL (1, 3, 0)},
|
||||
{"brl.dpnt.many.clr", BRL (1, 3, 1)},
|
||||
#undef BRL
|
||||
#undef BRLP
|
||||
#define BRL(a,b,c) X, OpPaWhaD (0xD, a, b, c), {B1, TGT64}, 0, 0, NULL
|
||||
#define BRLP(a,b,c) X, OpPaWhaD (0xD, a, b, c), {B1, TGT64}, PSEUDO, 0, NULL
|
||||
{"brl.call.sptk.few", BRL (0, 0, 0)},
|
||||
{"brl.call.sptk", BRLP (0, 0, 0)},
|
||||
{"brl.call.sptk.few.clr", BRL (0, 0, 1)},
|
||||
{"brl.call.sptk.clr", BRLP (0, 0, 1)},
|
||||
{"brl.call.spnt.few", BRL (0, 1, 0)},
|
||||
{"brl.call.spnt", BRLP (0, 1, 0)},
|
||||
{"brl.call.spnt.few.clr", BRL (0, 1, 1)},
|
||||
{"brl.call.spnt.clr", BRLP (0, 1, 1)},
|
||||
{"brl.call.dptk.few", BRL (0, 2, 0)},
|
||||
{"brl.call.dptk", BRLP (0, 2, 0)},
|
||||
{"brl.call.dptk.few.clr", BRL (0, 2, 1)},
|
||||
{"brl.call.dptk.clr", BRLP (0, 2, 1)},
|
||||
{"brl.call.dpnt.few", BRL (0, 3, 0)},
|
||||
{"brl.call.dpnt", BRLP (0, 3, 0)},
|
||||
{"brl.call.dpnt.few.clr", BRL (0, 3, 1)},
|
||||
{"brl.call.dpnt.clr", BRLP (0, 3, 1)},
|
||||
{"brl.call.sptk.many", BRL (1, 0, 0)},
|
||||
{"brl.call.sptk.many.clr", BRL (1, 0, 1)},
|
||||
{"brl.call.spnt.many", BRL (1, 1, 0)},
|
||||
{"brl.call.spnt.many.clr", BRL (1, 1, 1)},
|
||||
{"brl.call.dptk.many", BRL (1, 2, 0)},
|
||||
{"brl.call.dptk.many.clr", BRL (1, 2, 1)},
|
||||
{"brl.call.dpnt.many", BRL (1, 3, 0)},
|
||||
{"brl.call.dpnt.many.clr", BRL (1, 3, 1)},
|
||||
#undef BRL
|
||||
#undef BRLP
|
||||
{NULL, 0, 0, 0, 0, {0}, 0, 0, NULL}
|
||||
};
|
||||
|
||||
#undef X0
|
||||
#undef X
|
||||
|
||||
#undef bBtype
|
||||
#undef bD
|
||||
#undef bPa
|
||||
#undef bPr
|
||||
#undef bVc
|
||||
#undef bWha
|
||||
#undef bX3
|
||||
#undef bX6
|
||||
|
||||
#undef mBtype
|
||||
#undef mD
|
||||
#undef mPa
|
||||
#undef mPr
|
||||
#undef mVc
|
||||
#undef mWha
|
||||
#undef mX3
|
||||
#undef mX6
|
||||
|
||||
#undef OpX3X6
|
||||
#undef OpVc
|
||||
#undef OpPaWhaD
|
||||
#undef OpBtypePaWhaD
|
||||
#undef OpBtypePaWhaDPr
|
||||
@@ -1,727 +0,0 @@
|
||||
/* ia64-opc.c -- Functions to access the compacted opcode table
|
||||
Copyright 1999, 2000, 2001, 2003, 2005 Free Software Foundation, Inc.
|
||||
Written by Bob Manson of Cygnus Solutions, <manson@cygnus.com>
|
||||
|
||||
This file is part of GDB, GAS, and the GNU binutils.
|
||||
|
||||
GDB, GAS, and the GNU binutils are free software; you can redistribute
|
||||
them and/or modify them under the terms of the GNU General Public
|
||||
License as published by the Free Software Foundation; either version
|
||||
2, or (at your option) any later version.
|
||||
|
||||
GDB, GAS, and the GNU binutils are distributed in the hope that they
|
||||
will be useful, but WITHOUT ANY WARRANTY; without even the implied
|
||||
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
|
||||
the GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this file; see the file COPYING. If not, write to the
|
||||
Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
|
||||
02110-1301, USA. */
|
||||
|
||||
#include "ia64-asmtab.h"
|
||||
#include "ia64-asmtab.c"
|
||||
|
||||
static void get_opc_prefix (const char **, char *);
|
||||
static short int find_string_ent (const char *);
|
||||
static short int find_main_ent (short int);
|
||||
static short int find_completer (short int, short int, const char *);
|
||||
static ia64_insn apply_completer (ia64_insn, int);
|
||||
static int extract_op_bits (int, int, int);
|
||||
static int extract_op (int, int *, unsigned int *);
|
||||
static int opcode_verify (ia64_insn, int, enum ia64_insn_type);
|
||||
static int locate_opcode_ent (ia64_insn, enum ia64_insn_type);
|
||||
static struct ia64_opcode *make_ia64_opcode
|
||||
(ia64_insn, const char *, int, int);
|
||||
static struct ia64_opcode *ia64_find_matching_opcode
|
||||
(const char *, short int);
|
||||
|
||||
const struct ia64_templ_desc ia64_templ_desc[16] =
|
||||
{
|
||||
{ 0, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_I }, "MII" }, /* 0 */
|
||||
{ 2, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_I }, "MII" },
|
||||
{ 0, { IA64_UNIT_M, IA64_UNIT_L, IA64_UNIT_X }, "MLX" },
|
||||
{ 0, { 0, }, "-3-" },
|
||||
{ 0, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_I }, "MMI" }, /* 4 */
|
||||
{ 1, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_I }, "MMI" },
|
||||
{ 0, { IA64_UNIT_M, IA64_UNIT_F, IA64_UNIT_I }, "MFI" },
|
||||
{ 0, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_F }, "MMF" },
|
||||
{ 0, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_B }, "MIB" }, /* 8 */
|
||||
{ 0, { IA64_UNIT_M, IA64_UNIT_B, IA64_UNIT_B }, "MBB" },
|
||||
{ 0, { 0, }, "-a-" },
|
||||
{ 0, { IA64_UNIT_B, IA64_UNIT_B, IA64_UNIT_B }, "BBB" },
|
||||
{ 0, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_B }, "MMB" }, /* c */
|
||||
{ 0, { 0, }, "-d-" },
|
||||
{ 0, { IA64_UNIT_M, IA64_UNIT_F, IA64_UNIT_B }, "MFB" },
|
||||
{ 0, { 0, }, "-f-" },
|
||||
};
|
||||
|
||||
|
||||
/* Copy the prefix contained in *PTR (up to a '.' or a NUL) to DEST.
|
||||
PTR will be adjusted to point to the start of the next portion
|
||||
of the opcode, or at the NUL character. */
|
||||
|
||||
static void
|
||||
get_opc_prefix (const char **ptr, char *dest)
|
||||
{
|
||||
char *c = strchr (*ptr, '.');
|
||||
if (c != NULL)
|
||||
{
|
||||
memcpy (dest, *ptr, c - *ptr);
|
||||
dest[c - *ptr] = '\0';
|
||||
*ptr = c + 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
int l = strlen (*ptr);
|
||||
memcpy (dest, *ptr, l);
|
||||
dest[l] = '\0';
|
||||
*ptr += l;
|
||||
}
|
||||
}
|
||||
|
||||
/* Find the index of the entry in the string table corresponding to
|
||||
STR; return -1 if one does not exist. */
|
||||
|
||||
static short
|
||||
find_string_ent (const char *str)
|
||||
{
|
||||
short start = 0;
|
||||
short end = sizeof (ia64_strings) / sizeof (const char *);
|
||||
short i = (start + end) / 2;
|
||||
|
||||
if (strcmp (str, ia64_strings[end - 1]) > 0)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
while (start <= end)
|
||||
{
|
||||
int c = strcmp (str, ia64_strings[i]);
|
||||
if (c < 0)
|
||||
{
|
||||
end = i - 1;
|
||||
}
|
||||
else if (c == 0)
|
||||
{
|
||||
return i;
|
||||
}
|
||||
else
|
||||
{
|
||||
start = i + 1;
|
||||
}
|
||||
i = (start + end) / 2;
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Find the opcode in the main opcode table whose name is STRINGINDEX, or
|
||||
return -1 if one does not exist. */
|
||||
|
||||
static short
|
||||
find_main_ent (short nameindex)
|
||||
{
|
||||
short start = 0;
|
||||
short end = sizeof (main_table) / sizeof (struct ia64_main_table);
|
||||
short i = (start + end) / 2;
|
||||
|
||||
if (nameindex < main_table[0].name_index
|
||||
|| nameindex > main_table[end - 1].name_index)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
while (start <= end)
|
||||
{
|
||||
if (nameindex < main_table[i].name_index)
|
||||
{
|
||||
end = i - 1;
|
||||
}
|
||||
else if (nameindex == main_table[i].name_index)
|
||||
{
|
||||
while (i > 0 && main_table[i - 1].name_index == nameindex)
|
||||
{
|
||||
i--;
|
||||
}
|
||||
return i;
|
||||
}
|
||||
else
|
||||
{
|
||||
start = i + 1;
|
||||
}
|
||||
i = (start + end) / 2;
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Find the index of the entry in the completer table that is part of
|
||||
MAIN_ENT (starting from PREV_COMPLETER) that matches NAME, or
|
||||
return -1 if one does not exist. */
|
||||
|
||||
static short
|
||||
find_completer (short main_ent, short prev_completer, const char *name)
|
||||
{
|
||||
short name_index = find_string_ent (name);
|
||||
|
||||
if (name_index < 0)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (prev_completer == -1)
|
||||
{
|
||||
prev_completer = main_table[main_ent].completers;
|
||||
}
|
||||
else
|
||||
{
|
||||
prev_completer = completer_table[prev_completer].subentries;
|
||||
}
|
||||
|
||||
while (prev_completer != -1)
|
||||
{
|
||||
if (completer_table[prev_completer].name_index == name_index)
|
||||
{
|
||||
return prev_completer;
|
||||
}
|
||||
prev_completer = completer_table[prev_completer].alternative;
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Apply the completer referred to by COMPLETER_INDEX to OPCODE, and
|
||||
return the result. */
|
||||
|
||||
static ia64_insn
|
||||
apply_completer (ia64_insn opcode, int completer_index)
|
||||
{
|
||||
ia64_insn mask = completer_table[completer_index].mask;
|
||||
ia64_insn bits = completer_table[completer_index].bits;
|
||||
int shiftamt = (completer_table[completer_index].offset & 63);
|
||||
|
||||
mask = mask << shiftamt;
|
||||
bits = bits << shiftamt;
|
||||
opcode = (opcode & ~mask) | bits;
|
||||
return opcode;
|
||||
}
|
||||
|
||||
/* Extract BITS number of bits starting from OP_POINTER + BITOFFSET in
|
||||
the dis_table array, and return its value. (BITOFFSET is numbered
|
||||
starting from MSB to LSB, so a BITOFFSET of 0 indicates the MSB of the
|
||||
first byte in OP_POINTER.) */
|
||||
|
||||
static int
|
||||
extract_op_bits (int op_pointer, int bitoffset, int bits)
|
||||
{
|
||||
int res = 0;
|
||||
|
||||
op_pointer += (bitoffset / 8);
|
||||
|
||||
if (bitoffset % 8)
|
||||
{
|
||||
unsigned int op = dis_table[op_pointer++];
|
||||
int numb = 8 - (bitoffset % 8);
|
||||
int mask = (1 << numb) - 1;
|
||||
int bata = (bits < numb) ? bits : numb;
|
||||
int delta = numb - bata;
|
||||
|
||||
res = (res << bata) | ((op & mask) >> delta);
|
||||
bitoffset += bata;
|
||||
bits -= bata;
|
||||
}
|
||||
while (bits >= 8)
|
||||
{
|
||||
res = (res << 8) | (dis_table[op_pointer++] & 255);
|
||||
bits -= 8;
|
||||
}
|
||||
if (bits > 0)
|
||||
{
|
||||
unsigned int op = (dis_table[op_pointer++] & 255);
|
||||
res = (res << bits) | (op >> (8 - bits));
|
||||
}
|
||||
return res;
|
||||
}
|
||||
|
||||
/* Examine the state machine entry at OP_POINTER in the dis_table
|
||||
array, and extract its values into OPVAL and OP. The length of the
|
||||
state entry in bits is returned. */
|
||||
|
||||
static int
|
||||
extract_op (int op_pointer, int *opval, unsigned int *op)
|
||||
{
|
||||
int oplen = 5;
|
||||
|
||||
*op = dis_table[op_pointer];
|
||||
|
||||
if ((*op) & 0x40)
|
||||
{
|
||||
opval[0] = extract_op_bits (op_pointer, oplen, 5);
|
||||
oplen += 5;
|
||||
}
|
||||
switch ((*op) & 0x30)
|
||||
{
|
||||
case 0x10:
|
||||
{
|
||||
opval[1] = extract_op_bits (op_pointer, oplen, 8);
|
||||
oplen += 8;
|
||||
opval[1] += op_pointer;
|
||||
break;
|
||||
}
|
||||
case 0x20:
|
||||
{
|
||||
opval[1] = extract_op_bits (op_pointer, oplen, 16);
|
||||
if (! (opval[1] & 32768))
|
||||
{
|
||||
opval[1] += op_pointer;
|
||||
}
|
||||
oplen += 16;
|
||||
break;
|
||||
}
|
||||
case 0x30:
|
||||
{
|
||||
oplen--;
|
||||
opval[2] = extract_op_bits (op_pointer, oplen, 12);
|
||||
oplen += 12;
|
||||
opval[2] |= 32768;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (((*op) & 0x08) && (((*op) & 0x30) != 0x30))
|
||||
{
|
||||
opval[2] = extract_op_bits (op_pointer, oplen, 16);
|
||||
oplen += 16;
|
||||
if (! (opval[2] & 32768))
|
||||
{
|
||||
opval[2] += op_pointer;
|
||||
}
|
||||
}
|
||||
return oplen;
|
||||
}
|
||||
|
||||
/* Returns a non-zero value if the opcode in the main_table list at
|
||||
PLACE matches OPCODE and is of type TYPE. */
|
||||
|
||||
static int
|
||||
opcode_verify (ia64_insn opcode, int place, enum ia64_insn_type type)
|
||||
{
|
||||
if (main_table[place].opcode_type != type)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
if (main_table[place].flags
|
||||
& (IA64_OPCODE_F2_EQ_F3 | IA64_OPCODE_LEN_EQ_64MCNT))
|
||||
{
|
||||
const struct ia64_operand *o1, *o2;
|
||||
ia64_insn f2, f3;
|
||||
|
||||
if (main_table[place].flags & IA64_OPCODE_F2_EQ_F3)
|
||||
{
|
||||
o1 = elf64_ia64_operands + IA64_OPND_F2;
|
||||
o2 = elf64_ia64_operands + IA64_OPND_F3;
|
||||
(*o1->extract) (o1, opcode, &f2);
|
||||
(*o2->extract) (o2, opcode, &f3);
|
||||
if (f2 != f3)
|
||||
return 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
ia64_insn len, count;
|
||||
|
||||
/* length must equal 64-count: */
|
||||
o1 = elf64_ia64_operands + IA64_OPND_LEN6;
|
||||
o2 = elf64_ia64_operands + main_table[place].operands[2];
|
||||
(*o1->extract) (o1, opcode, &len);
|
||||
(*o2->extract) (o2, opcode, &count);
|
||||
if (len != 64 - count)
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Find an instruction entry in the ia64_dis_names array that matches
|
||||
opcode OPCODE and is of type TYPE. Returns either a positive index
|
||||
into the array, or a negative value if an entry for OPCODE could
|
||||
not be found. Checks all matches and returns the one with the highest
|
||||
priority. */
|
||||
|
||||
static int
|
||||
locate_opcode_ent (ia64_insn opcode, enum ia64_insn_type type)
|
||||
{
|
||||
int currtest[41];
|
||||
int bitpos[41];
|
||||
int op_ptr[41];
|
||||
int currstatenum = 0;
|
||||
short found_disent = -1;
|
||||
short found_priority = -1;
|
||||
|
||||
currtest[currstatenum] = 0;
|
||||
op_ptr[currstatenum] = 0;
|
||||
bitpos[currstatenum] = 40;
|
||||
|
||||
while (1)
|
||||
{
|
||||
int op_pointer = op_ptr[currstatenum];
|
||||
unsigned int op;
|
||||
int currbitnum = bitpos[currstatenum];
|
||||
int oplen;
|
||||
int opval[3] = {0};
|
||||
int next_op;
|
||||
int currbit;
|
||||
|
||||
oplen = extract_op (op_pointer, opval, &op);
|
||||
|
||||
bitpos[currstatenum] = currbitnum;
|
||||
|
||||
/* Skip opval[0] bits in the instruction. */
|
||||
if (op & 0x40)
|
||||
{
|
||||
currbitnum -= opval[0];
|
||||
}
|
||||
|
||||
/* The value of the current bit being tested. */
|
||||
currbit = opcode & (((ia64_insn) 1) << currbitnum) ? 1 : 0;
|
||||
next_op = -1;
|
||||
|
||||
/* We always perform the tests specified in the current state in
|
||||
a particular order, falling through to the next test if the
|
||||
previous one failed. */
|
||||
switch (currtest[currstatenum])
|
||||
{
|
||||
case 0:
|
||||
currtest[currstatenum]++;
|
||||
if (currbit == 0 && (op & 0x80))
|
||||
{
|
||||
/* Check for a zero bit. If this test solely checks for
|
||||
a zero bit, we can check for up to 8 consecutive zero
|
||||
bits (the number to check is specified by the lower 3
|
||||
bits in the state code.)
|
||||
|
||||
If the state instruction matches, we go to the very
|
||||
next state instruction; otherwise, try the next test. */
|
||||
|
||||
if ((op & 0xf8) == 0x80)
|
||||
{
|
||||
int count = op & 0x7;
|
||||
int x;
|
||||
|
||||
for (x = 0; x <= count; x++)
|
||||
{
|
||||
int i =
|
||||
opcode & (((ia64_insn) 1) << (currbitnum - x)) ? 1 : 0;
|
||||
if (i)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (x > count)
|
||||
{
|
||||
next_op = op_pointer + ((oplen + 7) / 8);
|
||||
currbitnum -= count;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else if (! currbit)
|
||||
{
|
||||
next_op = op_pointer + ((oplen + 7) / 8);
|
||||
break;
|
||||
}
|
||||
}
|
||||
/* FALLTHROUGH */
|
||||
case 1:
|
||||
/* If the bit in the instruction is one, go to the state
|
||||
instruction specified by opval[1]. */
|
||||
currtest[currstatenum]++;
|
||||
if (currbit && (op & 0x30) != 0 && ((op & 0x30) != 0x30))
|
||||
{
|
||||
next_op = opval[1];
|
||||
break;
|
||||
}
|
||||
/* FALLTHROUGH */
|
||||
case 2:
|
||||
/* Don't care. Skip the current bit and go to the state
|
||||
instruction specified by opval[2].
|
||||
|
||||
An encoding of 0x30 is special; this means that a 12-bit
|
||||
offset into the ia64_dis_names[] array is specified. */
|
||||
currtest[currstatenum]++;
|
||||
if ((op & 0x08) || ((op & 0x30) == 0x30))
|
||||
{
|
||||
next_op = opval[2];
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* If bit 15 is set in the address of the next state, an offset
|
||||
in the ia64_dis_names array was specified instead. We then
|
||||
check to see if an entry in the list of opcodes matches the
|
||||
opcode we were given; if so, we have succeeded. */
|
||||
|
||||
if ((next_op >= 0) && (next_op & 32768))
|
||||
{
|
||||
short disent = next_op & 32767;
|
||||
short priority = -1;
|
||||
|
||||
if (next_op > 65535)
|
||||
{
|
||||
abort ();
|
||||
}
|
||||
|
||||
/* Run through the list of opcodes to check, trying to find
|
||||
one that matches. */
|
||||
while (disent >= 0)
|
||||
{
|
||||
int place = ia64_dis_names[disent].insn_index;
|
||||
|
||||
priority = ia64_dis_names[disent].priority;
|
||||
|
||||
if (opcode_verify (opcode, place, type)
|
||||
&& priority > found_priority)
|
||||
{
|
||||
break;
|
||||
}
|
||||
if (ia64_dis_names[disent].next_flag)
|
||||
{
|
||||
disent++;
|
||||
}
|
||||
else
|
||||
{
|
||||
disent = -1;
|
||||
}
|
||||
}
|
||||
|
||||
if (disent >= 0)
|
||||
{
|
||||
found_disent = disent;
|
||||
found_priority = priority;
|
||||
}
|
||||
/* Try the next test in this state, regardless of whether a match
|
||||
was found. */
|
||||
next_op = -2;
|
||||
}
|
||||
|
||||
/* next_op == -1 is "back up to the previous state".
|
||||
next_op == -2 is "stay in this state and try the next test".
|
||||
Otherwise, transition to the state indicated by next_op. */
|
||||
|
||||
if (next_op == -1)
|
||||
{
|
||||
currstatenum--;
|
||||
if (currstatenum < 0)
|
||||
{
|
||||
return found_disent;
|
||||
}
|
||||
}
|
||||
else if (next_op >= 0)
|
||||
{
|
||||
currstatenum++;
|
||||
bitpos[currstatenum] = currbitnum - 1;
|
||||
op_ptr[currstatenum] = next_op;
|
||||
currtest[currstatenum] = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Construct an ia64_opcode entry based on OPCODE, NAME and PLACE. */
|
||||
|
||||
static struct ia64_opcode *
|
||||
make_ia64_opcode (ia64_insn opcode, const char *name, int place, int depind)
|
||||
{
|
||||
struct ia64_opcode *res =
|
||||
(struct ia64_opcode *) malloc (sizeof (struct ia64_opcode));
|
||||
res->name = strdup (name);
|
||||
res->type = main_table[place].opcode_type;
|
||||
res->num_outputs = main_table[place].num_outputs;
|
||||
res->opcode = opcode;
|
||||
res->mask = main_table[place].mask;
|
||||
res->operands[0] = main_table[place].operands[0];
|
||||
res->operands[1] = main_table[place].operands[1];
|
||||
res->operands[2] = main_table[place].operands[2];
|
||||
res->operands[3] = main_table[place].operands[3];
|
||||
res->operands[4] = main_table[place].operands[4];
|
||||
res->flags = main_table[place].flags;
|
||||
res->ent_index = place;
|
||||
res->dependencies = &op_dependencies[depind];
|
||||
return res;
|
||||
}
|
||||
|
||||
/* Determine the ia64_opcode entry for the opcode specified by INSN
|
||||
and TYPE. If a valid entry is not found, return NULL. */
|
||||
struct ia64_opcode *
|
||||
ia64_dis_opcode (ia64_insn insn, enum ia64_insn_type type)
|
||||
{
|
||||
int disent = locate_opcode_ent (insn, type);
|
||||
|
||||
if (disent < 0)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
else
|
||||
{
|
||||
unsigned int cb = ia64_dis_names[disent].completer_index;
|
||||
static char name[128];
|
||||
int place = ia64_dis_names[disent].insn_index;
|
||||
int ci = main_table[place].completers;
|
||||
ia64_insn tinsn = main_table[place].opcode;
|
||||
|
||||
strcpy (name, ia64_strings [main_table[place].name_index]);
|
||||
|
||||
while (cb)
|
||||
{
|
||||
if (cb & 1)
|
||||
{
|
||||
int cname = completer_table[ci].name_index;
|
||||
|
||||
tinsn = apply_completer (tinsn, ci);
|
||||
|
||||
if (ia64_strings[cname][0] != '\0')
|
||||
{
|
||||
strcat (name, ".");
|
||||
strcat (name, ia64_strings[cname]);
|
||||
}
|
||||
if (cb != 1)
|
||||
{
|
||||
ci = completer_table[ci].subentries;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
ci = completer_table[ci].alternative;
|
||||
}
|
||||
if (ci < 0)
|
||||
{
|
||||
abort ();
|
||||
}
|
||||
cb = cb >> 1;
|
||||
}
|
||||
if (tinsn != (insn & main_table[place].mask))
|
||||
{
|
||||
abort ();
|
||||
}
|
||||
return make_ia64_opcode (insn, name, place,
|
||||
completer_table[ci].dependencies);
|
||||
}
|
||||
}
|
||||
|
||||
/* Search the main_opcode table starting from PLACE for an opcode that
|
||||
matches NAME. Return NULL if one is not found. */
|
||||
|
||||
static struct ia64_opcode *
|
||||
ia64_find_matching_opcode (const char *name, short place)
|
||||
{
|
||||
char op[129];
|
||||
const char *suffix;
|
||||
short name_index;
|
||||
|
||||
if (strlen (name) > 128)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
suffix = name;
|
||||
get_opc_prefix (&suffix, op);
|
||||
name_index = find_string_ent (op);
|
||||
if (name_index < 0)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
while (main_table[place].name_index == name_index)
|
||||
{
|
||||
const char *curr_suffix = suffix;
|
||||
ia64_insn curr_insn = main_table[place].opcode;
|
||||
short completer = -1;
|
||||
|
||||
do {
|
||||
if (suffix[0] == '\0')
|
||||
{
|
||||
completer = find_completer (place, completer, suffix);
|
||||
}
|
||||
else
|
||||
{
|
||||
get_opc_prefix (&curr_suffix, op);
|
||||
completer = find_completer (place, completer, op);
|
||||
}
|
||||
if (completer != -1)
|
||||
{
|
||||
curr_insn = apply_completer (curr_insn, completer);
|
||||
}
|
||||
} while (completer != -1 && curr_suffix[0] != '\0');
|
||||
|
||||
if (completer != -1 && curr_suffix[0] == '\0'
|
||||
&& completer_table[completer].terminal_completer)
|
||||
{
|
||||
int depind = completer_table[completer].dependencies;
|
||||
return make_ia64_opcode (curr_insn, name, place, depind);
|
||||
}
|
||||
else
|
||||
{
|
||||
place++;
|
||||
}
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Find the next opcode after PREV_ENT that matches PREV_ENT, or return NULL
|
||||
if one does not exist.
|
||||
|
||||
It is the caller's responsibility to invoke ia64_free_opcode () to
|
||||
release any resources used by the returned entry. */
|
||||
|
||||
struct ia64_opcode *
|
||||
ia64_find_next_opcode (struct ia64_opcode *prev_ent)
|
||||
{
|
||||
return ia64_find_matching_opcode (prev_ent->name,
|
||||
prev_ent->ent_index + 1);
|
||||
}
|
||||
|
||||
/* Find the first opcode that matches NAME, or return NULL if it does
|
||||
not exist.
|
||||
|
||||
It is the caller's responsibility to invoke ia64_free_opcode () to
|
||||
release any resources used by the returned entry. */
|
||||
|
||||
struct ia64_opcode *
|
||||
ia64_find_opcode (const char *name)
|
||||
{
|
||||
char op[129];
|
||||
const char *suffix;
|
||||
short place;
|
||||
short name_index;
|
||||
|
||||
if (strlen (name) > 128)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
suffix = name;
|
||||
get_opc_prefix (&suffix, op);
|
||||
name_index = find_string_ent (op);
|
||||
if (name_index < 0)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
place = find_main_ent (name_index);
|
||||
|
||||
if (place < 0)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
return ia64_find_matching_opcode (name, place);
|
||||
}
|
||||
|
||||
/* Free any resources used by ENT. */
|
||||
void
|
||||
ia64_free_opcode (struct ia64_opcode *ent)
|
||||
{
|
||||
free ((void *)ent->name);
|
||||
free (ent);
|
||||
}
|
||||
|
||||
const struct ia64_dependency *
|
||||
ia64_find_dependency (int index)
|
||||
{
|
||||
index = DEP(index);
|
||||
|
||||
if (index < 0
|
||||
|| index >= (int)(sizeof(dependencies) / sizeof(dependencies[0])))
|
||||
return NULL;
|
||||
|
||||
return &dependencies[index];
|
||||
}
|
||||
@@ -1,133 +0,0 @@
|
||||
/* ia64-opc.h -- IA-64 opcode table.
|
||||
Copyright 1998, 1999, 2000, 2002, 2005, 2006
|
||||
Free Software Foundation, Inc.
|
||||
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
|
||||
|
||||
This file is part of GDB, GAS, and the GNU binutils.
|
||||
|
||||
GDB, GAS, and the GNU binutils are free software; you can redistribute
|
||||
them and/or modify them under the terms of the GNU General Public
|
||||
License as published by the Free Software Foundation; either version
|
||||
2, or (at your option) any later version.
|
||||
|
||||
GDB, GAS, and the GNU binutils are distributed in the hope that they
|
||||
will be useful, but WITHOUT ANY WARRANTY; without even the implied
|
||||
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
|
||||
the GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this file; see the file COPYING. If not, write to the
|
||||
Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
|
||||
02110-1301, USA. */
|
||||
|
||||
#ifndef IA64_OPC_H
|
||||
#define IA64_OPC_H
|
||||
|
||||
#include "ia64.h"
|
||||
|
||||
/* define a couple of abbreviations: */
|
||||
|
||||
#define bOp(x) (((ia64_insn) ((x) & 0xf)) << 37)
|
||||
#define mOp bOp (-1)
|
||||
#define Op(x) bOp (x), mOp
|
||||
|
||||
#define FIRST IA64_OPCODE_FIRST
|
||||
#define X_IN_MLX IA64_OPCODE_X_IN_MLX
|
||||
#define LAST IA64_OPCODE_LAST
|
||||
#define PRIV IA64_OPCODE_PRIV
|
||||
#define NO_PRED IA64_OPCODE_NO_PRED
|
||||
#define SLOT2 IA64_OPCODE_SLOT2
|
||||
#define PSEUDO IA64_OPCODE_PSEUDO
|
||||
#define F2_EQ_F3 IA64_OPCODE_F2_EQ_F3
|
||||
#define LEN_EQ_64MCNT IA64_OPCODE_LEN_EQ_64MCNT
|
||||
#define MOD_RRBS IA64_OPCODE_MOD_RRBS
|
||||
#define POSTINC IA64_OPCODE_POSTINC
|
||||
|
||||
#define AR_CCV IA64_OPND_AR_CCV
|
||||
#define AR_PFS IA64_OPND_AR_PFS
|
||||
#define AR_CSD IA64_OPND_AR_CSD
|
||||
#define C1 IA64_OPND_C1
|
||||
#define C8 IA64_OPND_C8
|
||||
#define C16 IA64_OPND_C16
|
||||
#define GR0 IA64_OPND_GR0
|
||||
#define IP IA64_OPND_IP
|
||||
#define PR IA64_OPND_PR
|
||||
#define PR_ROT IA64_OPND_PR_ROT
|
||||
#define PSR IA64_OPND_PSR
|
||||
#define PSR_L IA64_OPND_PSR_L
|
||||
#define PSR_UM IA64_OPND_PSR_UM
|
||||
|
||||
#define AR3 IA64_OPND_AR3
|
||||
#define B1 IA64_OPND_B1
|
||||
#define B2 IA64_OPND_B2
|
||||
#define CR3 IA64_OPND_CR3
|
||||
#define F1 IA64_OPND_F1
|
||||
#define F2 IA64_OPND_F2
|
||||
#define F3 IA64_OPND_F3
|
||||
#define F4 IA64_OPND_F4
|
||||
#define P1 IA64_OPND_P1
|
||||
#define P2 IA64_OPND_P2
|
||||
#define R1 IA64_OPND_R1
|
||||
#define R2 IA64_OPND_R2
|
||||
#define R3 IA64_OPND_R3
|
||||
#define R3_2 IA64_OPND_R3_2
|
||||
|
||||
#define CPUID_R3 IA64_OPND_CPUID_R3
|
||||
#define DBR_R3 IA64_OPND_DBR_R3
|
||||
#define DTR_R3 IA64_OPND_DTR_R3
|
||||
#define ITR_R3 IA64_OPND_ITR_R3
|
||||
#define IBR_R3 IA64_OPND_IBR_R3
|
||||
#define MR3 IA64_OPND_MR3
|
||||
#define MSR_R3 IA64_OPND_MSR_R3
|
||||
#define PKR_R3 IA64_OPND_PKR_R3
|
||||
#define PMC_R3 IA64_OPND_PMC_R3
|
||||
#define PMD_R3 IA64_OPND_PMD_R3
|
||||
#define RR_R3 IA64_OPND_RR_R3
|
||||
|
||||
#define CCNT5 IA64_OPND_CCNT5
|
||||
#define CNT2a IA64_OPND_CNT2a
|
||||
#define CNT2b IA64_OPND_CNT2b
|
||||
#define CNT2c IA64_OPND_CNT2c
|
||||
#define CNT5 IA64_OPND_CNT5
|
||||
#define CNT6 IA64_OPND_CNT6
|
||||
#define CPOS6a IA64_OPND_CPOS6a
|
||||
#define CPOS6b IA64_OPND_CPOS6b
|
||||
#define CPOS6c IA64_OPND_CPOS6c
|
||||
#define IMM1 IA64_OPND_IMM1
|
||||
#define IMM14 IA64_OPND_IMM14
|
||||
#define IMM17 IA64_OPND_IMM17
|
||||
#define IMM22 IA64_OPND_IMM22
|
||||
#define IMM44 IA64_OPND_IMM44
|
||||
#define SOF IA64_OPND_SOF
|
||||
#define SOL IA64_OPND_SOL
|
||||
#define SOR IA64_OPND_SOR
|
||||
#define IMM8 IA64_OPND_IMM8
|
||||
#define IMM8U4 IA64_OPND_IMM8U4
|
||||
#define IMM8M1 IA64_OPND_IMM8M1
|
||||
#define IMM8M1U4 IA64_OPND_IMM8M1U4
|
||||
#define IMM8M1U8 IA64_OPND_IMM8M1U8
|
||||
#define IMM9a IA64_OPND_IMM9a
|
||||
#define IMM9b IA64_OPND_IMM9b
|
||||
#define IMMU2 IA64_OPND_IMMU2
|
||||
#define IMMU21 IA64_OPND_IMMU21
|
||||
#define IMMU24 IA64_OPND_IMMU24
|
||||
#define IMMU62 IA64_OPND_IMMU62
|
||||
#define IMMU64 IA64_OPND_IMMU64
|
||||
#define IMMU5b IA64_OPND_IMMU5b
|
||||
#define IMMU7a IA64_OPND_IMMU7a
|
||||
#define IMMU7b IA64_OPND_IMMU7b
|
||||
#define IMMU9 IA64_OPND_IMMU9
|
||||
#define INC3 IA64_OPND_INC3
|
||||
#define LEN4 IA64_OPND_LEN4
|
||||
#define LEN6 IA64_OPND_LEN6
|
||||
#define MBTYPE4 IA64_OPND_MBTYPE4
|
||||
#define MHTYPE8 IA64_OPND_MHTYPE8
|
||||
#define POS6 IA64_OPND_POS6
|
||||
#define TAG13 IA64_OPND_TAG13
|
||||
#define TAG13b IA64_OPND_TAG13b
|
||||
#define TGT25 IA64_OPND_TGT25
|
||||
#define TGT25b IA64_OPND_TGT25b
|
||||
#define TGT25c IA64_OPND_TGT25c
|
||||
#define TGT64 IA64_OPND_TGT64
|
||||
|
||||
#endif
|
||||
@@ -1,396 +0,0 @@
|
||||
/* ia64.h -- Header file for ia64 opcode table
|
||||
Copyright (C) 1998, 1999, 2000, 2002, 2005, 2006
|
||||
Free Software Foundation, Inc.
|
||||
Contributed by David Mosberger-Tang <davidm@hpl.hp.com> */
|
||||
|
||||
#ifndef opcode_ia64_h
|
||||
#define opcode_ia64_h
|
||||
|
||||
#include <sys/types.h>
|
||||
|
||||
#include "dis-asm.h"
|
||||
|
||||
|
||||
typedef BFD_HOST_U_64_BIT ia64_insn;
|
||||
|
||||
enum ia64_insn_type
|
||||
{
|
||||
IA64_TYPE_NIL = 0, /* illegal type */
|
||||
IA64_TYPE_A, /* integer alu (I- or M-unit) */
|
||||
IA64_TYPE_I, /* non-alu integer (I-unit) */
|
||||
IA64_TYPE_M, /* memory (M-unit) */
|
||||
IA64_TYPE_B, /* branch (B-unit) */
|
||||
IA64_TYPE_F, /* floating-point (F-unit) */
|
||||
IA64_TYPE_X, /* long encoding (X-unit) */
|
||||
IA64_TYPE_DYN, /* Dynamic opcode */
|
||||
IA64_NUM_TYPES
|
||||
};
|
||||
|
||||
enum ia64_unit
|
||||
{
|
||||
IA64_UNIT_NIL = 0, /* illegal unit */
|
||||
IA64_UNIT_I, /* integer unit */
|
||||
IA64_UNIT_M, /* memory unit */
|
||||
IA64_UNIT_B, /* branching unit */
|
||||
IA64_UNIT_F, /* floating-point unit */
|
||||
IA64_UNIT_L, /* long "unit" */
|
||||
IA64_UNIT_X, /* may be integer or branch unit */
|
||||
IA64_NUM_UNITS
|
||||
};
|
||||
|
||||
/* Changes to this enumeration must be propagated to the operand table in
|
||||
bfd/cpu-ia64-opc.c
|
||||
*/
|
||||
enum ia64_opnd
|
||||
{
|
||||
IA64_OPND_NIL, /* no operand---MUST BE FIRST!*/
|
||||
|
||||
/* constants */
|
||||
IA64_OPND_AR_CSD, /* application register csd (ar.csd) */
|
||||
IA64_OPND_AR_CCV, /* application register ccv (ar.ccv) */
|
||||
IA64_OPND_AR_PFS, /* application register pfs (ar.pfs) */
|
||||
IA64_OPND_C1, /* the constant 1 */
|
||||
IA64_OPND_C8, /* the constant 8 */
|
||||
IA64_OPND_C16, /* the constant 16 */
|
||||
IA64_OPND_GR0, /* gr0 */
|
||||
IA64_OPND_IP, /* instruction pointer (ip) */
|
||||
IA64_OPND_PR, /* predicate register (pr) */
|
||||
IA64_OPND_PR_ROT, /* rotating predicate register (pr.rot) */
|
||||
IA64_OPND_PSR, /* processor status register (psr) */
|
||||
IA64_OPND_PSR_L, /* processor status register L (psr.l) */
|
||||
IA64_OPND_PSR_UM, /* processor status register UM (psr.um) */
|
||||
|
||||
/* register operands: */
|
||||
IA64_OPND_AR3, /* third application register # (bits 20-26) */
|
||||
IA64_OPND_B1, /* branch register # (bits 6-8) */
|
||||
IA64_OPND_B2, /* branch register # (bits 13-15) */
|
||||
IA64_OPND_CR3, /* third control register # (bits 20-26) */
|
||||
IA64_OPND_F1, /* first floating-point register # */
|
||||
IA64_OPND_F2, /* second floating-point register # */
|
||||
IA64_OPND_F3, /* third floating-point register # */
|
||||
IA64_OPND_F4, /* fourth floating-point register # */
|
||||
IA64_OPND_P1, /* first predicate # */
|
||||
IA64_OPND_P2, /* second predicate # */
|
||||
IA64_OPND_R1, /* first register # */
|
||||
IA64_OPND_R2, /* second register # */
|
||||
IA64_OPND_R3, /* third register # */
|
||||
IA64_OPND_R3_2, /* third register # (limited to gr0-gr3) */
|
||||
|
||||
/* memory operands: */
|
||||
IA64_OPND_MR3, /* memory at addr of third register # */
|
||||
|
||||
/* indirect operands: */
|
||||
IA64_OPND_CPUID_R3, /* cpuid[reg] */
|
||||
IA64_OPND_DBR_R3, /* dbr[reg] */
|
||||
IA64_OPND_DTR_R3, /* dtr[reg] */
|
||||
IA64_OPND_ITR_R3, /* itr[reg] */
|
||||
IA64_OPND_IBR_R3, /* ibr[reg] */
|
||||
IA64_OPND_MSR_R3, /* msr[reg] */
|
||||
IA64_OPND_PKR_R3, /* pkr[reg] */
|
||||
IA64_OPND_PMC_R3, /* pmc[reg] */
|
||||
IA64_OPND_PMD_R3, /* pmd[reg] */
|
||||
IA64_OPND_RR_R3, /* rr[reg] */
|
||||
|
||||
/* immediate operands: */
|
||||
IA64_OPND_CCNT5, /* 5-bit count (31 - bits 20-24) */
|
||||
IA64_OPND_CNT2a, /* 2-bit count (1 + bits 27-28) */
|
||||
IA64_OPND_CNT2b, /* 2-bit count (bits 27-28): 1, 2, 3 */
|
||||
IA64_OPND_CNT2c, /* 2-bit count (bits 30-31): 0, 7, 15, or 16 */
|
||||
IA64_OPND_CNT5, /* 5-bit count (bits 14-18) */
|
||||
IA64_OPND_CNT6, /* 6-bit count (bits 27-32) */
|
||||
IA64_OPND_CPOS6a, /* 6-bit count (63 - bits 20-25) */
|
||||
IA64_OPND_CPOS6b, /* 6-bit count (63 - bits 14-19) */
|
||||
IA64_OPND_CPOS6c, /* 6-bit count (63 - bits 31-36) */
|
||||
IA64_OPND_IMM1, /* signed 1-bit immediate (bit 36) */
|
||||
IA64_OPND_IMMU2, /* unsigned 2-bit immediate (bits 13-14) */
|
||||
IA64_OPND_IMMU5b, /* unsigned 5-bit immediate (32 + bits 14-18) */
|
||||
IA64_OPND_IMMU7a, /* unsigned 7-bit immediate (bits 13-19) */
|
||||
IA64_OPND_IMMU7b, /* unsigned 7-bit immediate (bits 20-26) */
|
||||
IA64_OPND_SOF, /* 8-bit stack frame size */
|
||||
IA64_OPND_SOL, /* 8-bit size of locals */
|
||||
IA64_OPND_SOR, /* 6-bit number of rotating registers (scaled by 8) */
|
||||
IA64_OPND_IMM8, /* signed 8-bit immediate (bits 13-19 & 36) */
|
||||
IA64_OPND_IMM8U4, /* cmp4*u signed 8-bit immediate (bits 13-19 & 36) */
|
||||
IA64_OPND_IMM8M1, /* signed 8-bit immediate -1 (bits 13-19 & 36) */
|
||||
IA64_OPND_IMM8M1U4, /* cmp4*u signed 8-bit immediate -1 (bits 13-19 & 36)*/
|
||||
IA64_OPND_IMM8M1U8, /* cmp*u signed 8-bit immediate -1 (bits 13-19 & 36) */
|
||||
IA64_OPND_IMMU9, /* unsigned 9-bit immediate (bits 33-34, 20-26) */
|
||||
IA64_OPND_IMM9a, /* signed 9-bit immediate (bits 6-12, 27, 36) */
|
||||
IA64_OPND_IMM9b, /* signed 9-bit immediate (bits 13-19, 27, 36) */
|
||||
IA64_OPND_IMM14, /* signed 14-bit immediate (bits 13-19, 27-32, 36) */
|
||||
IA64_OPND_IMM17, /* signed 17-bit immediate (2*bits 6-12, 24-31, 36) */
|
||||
IA64_OPND_IMMU21, /* unsigned 21-bit immediate (bits 6-25, 36) */
|
||||
IA64_OPND_IMM22, /* signed 22-bit immediate (bits 13-19, 22-36) */
|
||||
IA64_OPND_IMMU24, /* unsigned 24-bit immediate (bits 6-26, 31-32, 36) */
|
||||
IA64_OPND_IMM44, /* signed 44-bit immediate (2^16*bits 6-32, 36) */
|
||||
IA64_OPND_IMMU62, /* unsigned 62-bit immediate */
|
||||
IA64_OPND_IMMU64, /* unsigned 64-bit immediate (lotsa bits...) */
|
||||
IA64_OPND_INC3, /* signed 3-bit (bits 13-15): +/-1, 4, 8, 16 */
|
||||
IA64_OPND_LEN4, /* 4-bit count (bits 27-30 + 1) */
|
||||
IA64_OPND_LEN6, /* 6-bit count (bits 27-32 + 1) */
|
||||
IA64_OPND_MBTYPE4, /* 4-bit mux type (bits 20-23) */
|
||||
IA64_OPND_MHTYPE8, /* 8-bit mux type (bits 20-27) */
|
||||
IA64_OPND_POS6, /* 6-bit count (bits 14-19) */
|
||||
IA64_OPND_TAG13, /* signed 13-bit tag (ip + 16*bits 6-12, 33-34) */
|
||||
IA64_OPND_TAG13b, /* signed 13-bit tag (ip + 16*bits 24-32) */
|
||||
IA64_OPND_TGT25, /* signed 25-bit (ip + 16*bits 6-25, 36) */
|
||||
IA64_OPND_TGT25b, /* signed 25-bit (ip + 16*bits 6-12, 20-32, 36) */
|
||||
IA64_OPND_TGT25c, /* signed 25-bit (ip + 16*bits 13-32, 36) */
|
||||
IA64_OPND_TGT64, /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */
|
||||
IA64_OPND_LDXMOV, /* any symbol, generates R_IA64_LDXMOV. */
|
||||
|
||||
IA64_OPND_COUNT /* # of operand types (MUST BE LAST!) */
|
||||
};
|
||||
|
||||
enum ia64_dependency_mode
|
||||
{
|
||||
IA64_DV_RAW,
|
||||
IA64_DV_WAW,
|
||||
IA64_DV_WAR,
|
||||
};
|
||||
|
||||
enum ia64_dependency_semantics
|
||||
{
|
||||
IA64_DVS_NONE,
|
||||
IA64_DVS_IMPLIED,
|
||||
IA64_DVS_IMPLIEDF,
|
||||
IA64_DVS_DATA,
|
||||
IA64_DVS_INSTR,
|
||||
IA64_DVS_SPECIFIC,
|
||||
IA64_DVS_STOP,
|
||||
IA64_DVS_OTHER,
|
||||
};
|
||||
|
||||
enum ia64_resource_specifier
|
||||
{
|
||||
IA64_RS_ANY,
|
||||
IA64_RS_AR_K,
|
||||
IA64_RS_AR_UNAT,
|
||||
IA64_RS_AR, /* 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111 */
|
||||
IA64_RS_ARb, /* 48-63, 112-127 */
|
||||
IA64_RS_BR,
|
||||
IA64_RS_CFM,
|
||||
IA64_RS_CPUID,
|
||||
IA64_RS_CR_IRR,
|
||||
IA64_RS_CR_LRR,
|
||||
IA64_RS_CR, /* 3-7,10-15,18,26-63,75-79,82-127 */
|
||||
IA64_RS_DBR,
|
||||
IA64_RS_FR,
|
||||
IA64_RS_FRb,
|
||||
IA64_RS_GR0,
|
||||
IA64_RS_GR,
|
||||
IA64_RS_IBR,
|
||||
IA64_RS_INSERVICE, /* CR[EOI] or CR[IVR] */
|
||||
IA64_RS_MSR,
|
||||
IA64_RS_PKR,
|
||||
IA64_RS_PMC,
|
||||
IA64_RS_PMD,
|
||||
IA64_RS_PR, /* non-rotating, 1-15 */
|
||||
IA64_RS_PRr, /* rotating, 16-62 */
|
||||
IA64_RS_PR63,
|
||||
IA64_RS_RR,
|
||||
|
||||
IA64_RS_ARX, /* ARs not in RS_AR or RS_ARb */
|
||||
IA64_RS_CRX, /* CRs not in RS_CR */
|
||||
IA64_RS_PSR, /* PSR bits */
|
||||
IA64_RS_RSE, /* implementation-specific RSE resources */
|
||||
IA64_RS_AR_FPSR,
|
||||
};
|
||||
|
||||
enum ia64_rse_resource
|
||||
{
|
||||
IA64_RSE_N_STACKED_PHYS,
|
||||
IA64_RSE_BOF,
|
||||
IA64_RSE_STORE_REG,
|
||||
IA64_RSE_LOAD_REG,
|
||||
IA64_RSE_BSPLOAD,
|
||||
IA64_RSE_RNATBITINDEX,
|
||||
IA64_RSE_CFLE,
|
||||
IA64_RSE_NDIRTY,
|
||||
};
|
||||
|
||||
/* Information about a given resource dependency */
|
||||
struct ia64_dependency
|
||||
{
|
||||
/* Name of the resource */
|
||||
const char *name;
|
||||
/* Does this dependency need further specification? */
|
||||
enum ia64_resource_specifier specifier;
|
||||
/* Mode of dependency */
|
||||
enum ia64_dependency_mode mode;
|
||||
/* Dependency semantics */
|
||||
enum ia64_dependency_semantics semantics;
|
||||
/* Register index, if applicable (distinguishes AR, CR, and PSR deps) */
|
||||
#define REG_NONE (-1)
|
||||
int regindex;
|
||||
/* Special info on semantics */
|
||||
const char *info;
|
||||
};
|
||||
|
||||
/* Two arrays of indexes into the ia64_dependency table.
|
||||
chks are dependencies to check for conflicts when an opcode is
|
||||
encountered; regs are dependencies to register (mark as used) when an
|
||||
opcode is used. chks correspond to readers (RAW) or writers (WAW or
|
||||
WAR) of a resource, while regs correspond to writers (RAW or WAW) and
|
||||
readers (WAR) of a resource. */
|
||||
struct ia64_opcode_dependency
|
||||
{
|
||||
int nchks;
|
||||
const unsigned short *chks;
|
||||
int nregs;
|
||||
const unsigned short *regs;
|
||||
};
|
||||
|
||||
/* encode/extract the note/index for a dependency */
|
||||
#define RDEP(N,X) (((N)<<11)|(X))
|
||||
#define NOTE(X) (((X)>>11)&0x1F)
|
||||
#define DEP(X) ((X)&0x7FF)
|
||||
|
||||
/* A template descriptor describes the execution units that are active
|
||||
for each of the three slots. It also specifies the location of
|
||||
instruction group boundaries that may be present between two slots. */
|
||||
struct ia64_templ_desc
|
||||
{
|
||||
int group_boundary; /* 0=no boundary, 1=between slot 0 & 1, etc. */
|
||||
enum ia64_unit exec_unit[3];
|
||||
const char *name;
|
||||
};
|
||||
|
||||
/* The opcode table is an array of struct ia64_opcode. */
|
||||
|
||||
struct ia64_opcode
|
||||
{
|
||||
/* The opcode name. */
|
||||
const char *name;
|
||||
|
||||
/* The type of the instruction: */
|
||||
enum ia64_insn_type type;
|
||||
|
||||
/* Number of output operands: */
|
||||
int num_outputs;
|
||||
|
||||
/* The opcode itself. Those bits which will be filled in with
|
||||
operands are zeroes. */
|
||||
ia64_insn opcode;
|
||||
|
||||
/* The opcode mask. This is used by the disassembler. This is a
|
||||
mask containing ones indicating those bits which must match the
|
||||
opcode field, and zeroes indicating those bits which need not
|
||||
match (and are presumably filled in by operands). */
|
||||
ia64_insn mask;
|
||||
|
||||
/* An array of operand codes. Each code is an index into the
|
||||
operand table. They appear in the order which the operands must
|
||||
appear in assembly code, and are terminated by a zero. */
|
||||
enum ia64_opnd operands[5];
|
||||
|
||||
/* One bit flags for the opcode. These are primarily used to
|
||||
indicate specific processors and environments support the
|
||||
instructions. The defined values are listed below. */
|
||||
unsigned int flags;
|
||||
|
||||
/* Used by ia64_find_next_opcode (). */
|
||||
short ent_index;
|
||||
|
||||
/* Opcode dependencies. */
|
||||
const struct ia64_opcode_dependency *dependencies;
|
||||
};
|
||||
|
||||
/* Values defined for the flags field of a struct ia64_opcode. */
|
||||
|
||||
#define IA64_OPCODE_FIRST (1<<0) /* must be first in an insn group */
|
||||
#define IA64_OPCODE_X_IN_MLX (1<<1) /* insn is allowed in X slot of MLX */
|
||||
#define IA64_OPCODE_LAST (1<<2) /* must be last in an insn group */
|
||||
#define IA64_OPCODE_PRIV (1<<3) /* privileged instruct */
|
||||
#define IA64_OPCODE_SLOT2 (1<<4) /* insn allowed in slot 2 only */
|
||||
#define IA64_OPCODE_NO_PRED (1<<5) /* insn cannot be predicated */
|
||||
#define IA64_OPCODE_PSEUDO (1<<6) /* insn is a pseudo-op */
|
||||
#define IA64_OPCODE_F2_EQ_F3 (1<<7) /* constraint: F2 == F3 */
|
||||
#define IA64_OPCODE_LEN_EQ_64MCNT (1<<8) /* constraint: LEN == 64-CNT */
|
||||
#define IA64_OPCODE_MOD_RRBS (1<<9) /* modifies all rrbs in CFM */
|
||||
#define IA64_OPCODE_POSTINC (1<<10) /* postincrement MR3 operand */
|
||||
|
||||
/* A macro to extract the major opcode from an instruction. */
|
||||
#define IA64_OP(i) (((i) >> 37) & 0xf)
|
||||
|
||||
enum ia64_operand_class
|
||||
{
|
||||
IA64_OPND_CLASS_CST, /* constant */
|
||||
IA64_OPND_CLASS_REG, /* register */
|
||||
IA64_OPND_CLASS_IND, /* indirect register */
|
||||
IA64_OPND_CLASS_ABS, /* absolute value */
|
||||
IA64_OPND_CLASS_REL, /* IP-relative value */
|
||||
};
|
||||
|
||||
/* The operands table is an array of struct ia64_operand. */
|
||||
|
||||
struct ia64_operand
|
||||
{
|
||||
enum ia64_operand_class class;
|
||||
|
||||
/* Set VALUE as the operand bits for the operand of type SELF in the
|
||||
instruction pointed to by CODE. If an error occurs, *CODE is not
|
||||
modified and the returned string describes the cause of the
|
||||
error. If no error occurs, NULL is returned. */
|
||||
const char *(*insert) (const struct ia64_operand *self, ia64_insn value,
|
||||
ia64_insn *code);
|
||||
|
||||
/* Extract the operand bits for an operand of type SELF from
|
||||
instruction CODE store them in *VALUE. If an error occurs, the
|
||||
cause of the error is described by the string returned. If no
|
||||
error occurs, NULL is returned. */
|
||||
const char *(*extract) (const struct ia64_operand *self, ia64_insn code,
|
||||
ia64_insn *value);
|
||||
|
||||
/* A string whose meaning depends on the operand class. */
|
||||
|
||||
const char *str;
|
||||
|
||||
struct bit_field
|
||||
{
|
||||
/* The number of bits in the operand. */
|
||||
int bits;
|
||||
|
||||
/* How far the operand is left shifted in the instruction. */
|
||||
int shift;
|
||||
}
|
||||
field[4]; /* no operand has more than this many bit-fields */
|
||||
|
||||
unsigned int flags;
|
||||
|
||||
const char *desc; /* brief description */
|
||||
};
|
||||
|
||||
/* Values defined for the flags field of a struct ia64_operand. */
|
||||
|
||||
/* Disassemble as signed decimal (instead of hex): */
|
||||
#define IA64_OPND_FLAG_DECIMAL_SIGNED (1<<0)
|
||||
/* Disassemble as unsigned decimal (instead of hex): */
|
||||
#define IA64_OPND_FLAG_DECIMAL_UNSIGNED (1<<1)
|
||||
|
||||
extern const struct ia64_templ_desc ia64_templ_desc[16];
|
||||
|
||||
/* The tables are sorted by major opcode number and are otherwise in
|
||||
the order in which the disassembler should consider instructions. */
|
||||
extern struct ia64_opcode ia64_opcodes_a[];
|
||||
extern struct ia64_opcode ia64_opcodes_i[];
|
||||
extern struct ia64_opcode ia64_opcodes_m[];
|
||||
extern struct ia64_opcode ia64_opcodes_b[];
|
||||
extern struct ia64_opcode ia64_opcodes_f[];
|
||||
extern struct ia64_opcode ia64_opcodes_d[];
|
||||
|
||||
|
||||
extern struct ia64_opcode *ia64_find_opcode (const char *name);
|
||||
extern struct ia64_opcode *ia64_find_next_opcode (struct ia64_opcode *ent);
|
||||
|
||||
extern struct ia64_opcode *ia64_dis_opcode (ia64_insn insn,
|
||||
enum ia64_insn_type type);
|
||||
|
||||
extern void ia64_free_opcode (struct ia64_opcode *ent);
|
||||
extern const struct ia64_dependency *ia64_find_dependency (int index);
|
||||
|
||||
/* To avoid circular library dependencies, this array is implemented
|
||||
in bfd/cpu-ia64-opc.c: */
|
||||
extern const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT];
|
||||
|
||||
#endif /* opcode_ia64_h */
|
||||
File diff suppressed because it is too large.
Load diff