mirror of
https://github.com/xen-project/xen.git
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xen/riscv: introduce setup_initial_pages
The idea was taken from xvisor but the following changes
were done:
* Use only a minimal part of the code enough to enable MMU
* rename {_}setup_initial_pagetables functions
* add an argument for setup_initial_mapping to have
an opportunity to make set PTE flags.
* update setup_initial_pagetables function to map sections
with correct PTE flags.
* Rewrite enable_mmu() to C.
* map linker addresses range to load addresses range without
1:1 mapping. It will be 1:1 only in case when
load_start_addr is equal to linker_start_addr.
* add safety checks such as:
* Xen size is less than page size
* linker addresses range doesn't overlap load addresses
range
* Rework macros {THIRD,SECOND,FIRST,ZEROETH}_{SHIFT,MASK}
* change PTE_LEAF_DEFAULT to RW instead of RWX.
* Remove phys_offset as it is not used now
* Remove alignment of {map, pa}_start &= XEN_PT_LEVEL_MAP_MASK(0);
in setup_inital_mapping() as they should be already aligned.
Make a check that {map_pa}_start are aligned.
* Remove clear_pagetables() as initial pagetables will be
zeroed during bss initialization
* Remove __attribute__((section(".entry")) for setup_initial_pagetables()
as there is no such section in xen.lds.S
* Update the argument of pte_is_valid() to "const pte_t *p"
* Add check that Xen's load address is aligned at 4k boundary
* Refactor setup_initial_pagetables() so it is mapping linker
address range to load address range. After setup needed
permissions for specific section ( such as .text, .rodata, etc )
otherwise RW permission will be set by default.
* Add function to check that requested SATP_MODE is supported
Origin: git@github.com:xvisor/xvisor.git 9be2fdd7
Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Bobby Eshleman <bobbyeshleman@gmail.com>
This commit is contained in:
Oleksii Kurochko authored and Jan Beulich committed
1 parent
efadb18dd5
commit
e66003e7be
10 files changed
+403
-1
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@@ -1,5 +1,6 @@
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obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
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obj-y += entry.o
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obj-y += mm.o
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obj-$(CONFIG_RISCV_64) += riscv64/
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obj-y += sbi.o
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obj-y += setup.o
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@@ -75,12 +75,24 @@
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name:
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#endif
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#define XEN_VIRT_START _AT(UL, 0x80200000)
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#ifdef CONFIG_RISCV_64
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#define XEN_VIRT_START 0xFFFFFFFFC0000000 /* (_AC(-1, UL) + 1 - GB(1)) */
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#else
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#error "RV32 isn't supported"
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#endif
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#define SMP_CACHE_BYTES (1 << 6)
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#define STACK_SIZE PAGE_SIZE
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#ifdef CONFIG_RISCV_64
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#define CONFIG_PAGING_LEVELS 3
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#define RV_STAGE1_MODE SATP_MODE_SV39
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#else
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#define CONFIG_PAGING_LEVELS 2
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#define RV_STAGE1_MODE SATP_MODE_SV32
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#endif
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#endif /* __RISCV_CONFIG_H__ */
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/*
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* Local variables:
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@@ -0,0 +1,11 @@
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#ifndef __ASM_CURRENT_H
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#define __ASM_CURRENT_H
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#define switch_stack_and_jump(stack, fn) do { \
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asm volatile ( \
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"mv sp, %0\n" \
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"j " #fn :: "r" (stack), "X" (fn) : "memory" ); \
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unreachable(); \
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} while ( false )
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#endif /* __ASM_CURRENT_H */
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@@ -0,0 +1,14 @@
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#ifndef _ASM_RISCV_MM_H
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#define _ASM_RISCV_MM_H
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#include <asm/page-bits.h>
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#define pfn_to_paddr(pfn) ((paddr_t)(pfn) << PAGE_SHIFT)
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#define paddr_to_pfn(pa) ((unsigned long)((pa) >> PAGE_SHIFT))
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void setup_initial_pagetables(void);
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void enable_mmu(void);
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void cont_after_mmu_is_enabled(void);
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#endif /* _ASM_RISCV_MM_H */
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@@ -4,4 +4,14 @@
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#define PAGE_SHIFT 12 /* 4 KiB Pages */
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#define PADDR_BITS 56 /* 44-bit PPN */
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#ifdef CONFIG_RISCV_64
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#define PAGETABLE_ORDER (9)
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#else /* CONFIG_RISCV_32 */
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#define PAGETABLE_ORDER (10)
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#endif
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#define PAGETABLE_ENTRIES (1 << PAGETABLE_ORDER)
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#define PTE_PPN_SHIFT 10
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#endif /* __RISCV_PAGE_BITS_H__ */
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@@ -0,0 +1,61 @@
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#ifndef _ASM_RISCV_PAGE_H
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#define _ASM_RISCV_PAGE_H
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#include <xen/const.h>
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#include <xen/types.h>
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#include <asm/mm.h>
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#include <asm/page-bits.h>
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#define VPN_MASK (PAGETABLE_ENTRIES - 1UL)
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#define XEN_PT_LEVEL_ORDER(lvl) ((lvl) * PAGETABLE_ORDER)
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#define XEN_PT_LEVEL_SHIFT(lvl) (XEN_PT_LEVEL_ORDER(lvl) + PAGE_SHIFT)
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#define XEN_PT_LEVEL_SIZE(lvl) (_AT(paddr_t, 1) << XEN_PT_LEVEL_SHIFT(lvl))
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#define XEN_PT_LEVEL_MAP_MASK(lvl) (~(XEN_PT_LEVEL_SIZE(lvl) - 1))
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#define XEN_PT_LEVEL_MASK(lvl) (VPN_MASK << XEN_PT_LEVEL_SHIFT(lvl))
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#define PTE_VALID BIT(0, UL)
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#define PTE_READABLE BIT(1, UL)
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#define PTE_WRITABLE BIT(2, UL)
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#define PTE_EXECUTABLE BIT(3, UL)
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#define PTE_USER BIT(4, UL)
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#define PTE_GLOBAL BIT(5, UL)
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#define PTE_ACCESSED BIT(6, UL)
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#define PTE_DIRTY BIT(7, UL)
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#define PTE_RSW (BIT(8, UL) | BIT(9, UL))
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#define PTE_LEAF_DEFAULT (PTE_VALID | PTE_READABLE | PTE_WRITABLE)
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#define PTE_TABLE (PTE_VALID)
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/* Calculate the offsets into the pagetables for a given VA */
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#define pt_linear_offset(lvl, va) ((va) >> XEN_PT_LEVEL_SHIFT(lvl))
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#define pt_index(lvl, va) (pt_linear_offset((lvl), (va)) & VPN_MASK)
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/* Page Table entry */
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typedef struct {
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#ifdef CONFIG_RISCV_64
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uint64_t pte;
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#else
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uint32_t pte;
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#endif
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} pte_t;
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static inline pte_t paddr_to_pte(paddr_t paddr,
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unsigned int permissions)
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{
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return (pte_t) { .pte = (paddr_to_pfn(paddr) << PTE_PPN_SHIFT) | permissions };
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}
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static inline paddr_t pte_to_paddr(pte_t pte)
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{
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return pfn_to_paddr(pte.pte >> PTE_PPN_SHIFT);
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}
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static inline bool pte_is_valid(pte_t p)
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{
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return p.pte & PTE_VALID;
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}
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#endif /* _ASM_RISCV_PAGE_H */
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@@ -69,6 +69,11 @@ static inline void die(void)
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wfi();
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}
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static inline void sfence_vma(void)
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{
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asm volatile ( "sfence.vma" ::: "memory" );
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}
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_RISCV_PROCESSOR_H */
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@@ -0,0 +1,275 @@
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#include <xen/compiler.h>
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#include <xen/init.h>
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#include <xen/kernel.h>
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#include <xen/pfn.h>
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#include <asm/early_printk.h>
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#include <asm/csr.h>
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#include <asm/current.h>
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#include <asm/mm.h>
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#include <asm/page.h>
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#include <asm/processor.h>
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struct mmu_desc {
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unsigned int num_levels;
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unsigned int pgtbl_count;
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pte_t *next_pgtbl;
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pte_t *pgtbl_base;
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};
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extern unsigned char cpu0_boot_stack[STACK_SIZE];
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#define PHYS_OFFSET ((unsigned long)_start - XEN_VIRT_START)
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#define LOAD_TO_LINK(addr) ((addr) - PHYS_OFFSET)
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#define LINK_TO_LOAD(addr) ((addr) + PHYS_OFFSET)
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/*
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* It is expected that Xen won't be more then 2 MB.
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* The check in xen.lds.S guarantees that.
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* At least 3 page tables (in case of Sv39 ) are needed to cover 2 MB.
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* One for each page level table with PAGE_SIZE = 4 Kb.
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*
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* One L0 page table can cover 2 MB(512 entries of one page table * PAGE_SIZE).
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*
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* It might be needed one more page table in case when Xen load address
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* isn't 2 MB aligned.
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*/
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#define PGTBL_INITIAL_COUNT ((CONFIG_PAGING_LEVELS - 1) + 1)
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pte_t __section(".bss.page_aligned") __aligned(PAGE_SIZE)
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stage1_pgtbl_root[PAGETABLE_ENTRIES];
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pte_t __section(".bss.page_aligned") __aligned(PAGE_SIZE)
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stage1_pgtbl_nonroot[PGTBL_INITIAL_COUNT * PAGETABLE_ENTRIES];
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#define HANDLE_PGTBL(curr_lvl_num) \
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index = pt_index(curr_lvl_num, page_addr); \
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if ( pte_is_valid(pgtbl[index]) ) \
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{ \
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/* Find L{ 0-3 } table */ \
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pgtbl = (pte_t *)pte_to_paddr(pgtbl[index]); \
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} \
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else \
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{ \
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/* Allocate new L{0-3} page table */ \
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if ( mmu_desc->pgtbl_count == PGTBL_INITIAL_COUNT ) \
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{ \
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early_printk("(XEN) No initial table available\n"); \
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/* panic(), BUG() or ASSERT() aren't ready now. */ \
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die(); \
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} \
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mmu_desc->pgtbl_count++; \
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pgtbl[index] = paddr_to_pte((unsigned long)mmu_desc->next_pgtbl, \
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PTE_VALID); \
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pgtbl = mmu_desc->next_pgtbl; \
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mmu_desc->next_pgtbl += PAGETABLE_ENTRIES; \
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}
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static void __init setup_initial_mapping(struct mmu_desc *mmu_desc,
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unsigned long map_start,
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unsigned long map_end,
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unsigned long pa_start)
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{
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unsigned int index;
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pte_t *pgtbl;
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unsigned long page_addr;
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if ( (unsigned long)_start % XEN_PT_LEVEL_SIZE(0) )
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{
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early_printk("(XEN) Xen should be loaded at 4k boundary\n");
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die();
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}
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if ( (map_start & ~XEN_PT_LEVEL_MAP_MASK(0)) ||
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(pa_start & ~XEN_PT_LEVEL_MAP_MASK(0)) )
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{
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early_printk("(XEN) map and pa start addresses should be aligned\n");
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/* panic(), BUG() or ASSERT() aren't ready now. */
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die();
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}
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for ( page_addr = map_start;
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page_addr < map_end;
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page_addr += XEN_PT_LEVEL_SIZE(0) )
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{
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pgtbl = mmu_desc->pgtbl_base;
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switch ( mmu_desc->num_levels )
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{
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case 4: /* Level 3 */
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HANDLE_PGTBL(3);
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case 3: /* Level 2 */
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HANDLE_PGTBL(2);
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case 2: /* Level 1 */
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HANDLE_PGTBL(1);
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case 1: /* Level 0 */
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{
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unsigned long paddr = (page_addr - map_start) + pa_start;
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unsigned int permissions = PTE_LEAF_DEFAULT;
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pte_t pte_to_be_written;
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index = pt_index(0, page_addr);
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if ( is_kernel_text(LINK_TO_LOAD(page_addr)) ||
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is_kernel_inittext(LINK_TO_LOAD(page_addr)) )
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permissions =
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PTE_EXECUTABLE | PTE_READABLE | PTE_VALID;
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if ( is_kernel_rodata(LINK_TO_LOAD(page_addr)) )
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permissions = PTE_READABLE | PTE_VALID;
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pte_to_be_written = paddr_to_pte(paddr, permissions);
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if ( !pte_is_valid(pgtbl[index]) )
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pgtbl[index] = pte_to_be_written;
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else
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{
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if ( (pgtbl[index].pte ^ pte_to_be_written.pte) &
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~(PTE_DIRTY | PTE_ACCESSED) )
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{
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early_printk("PTE overridden has occurred\n");
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/* panic(), <asm/bug.h> aren't ready now. */
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die();
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}
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}
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}
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}
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}
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}
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#undef HANDLE_PGTBL
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static bool __init check_pgtbl_mode_support(struct mmu_desc *mmu_desc,
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unsigned long load_start)
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{
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bool is_mode_supported = false;
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unsigned int index;
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unsigned int page_table_level = (mmu_desc->num_levels - 1);
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unsigned level_map_mask = XEN_PT_LEVEL_MAP_MASK(page_table_level);
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unsigned long aligned_load_start = load_start & level_map_mask;
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unsigned long aligned_page_size = XEN_PT_LEVEL_SIZE(page_table_level);
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unsigned long xen_size = (unsigned long)(_end - start);
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if ( (load_start + xen_size) > (aligned_load_start + aligned_page_size) )
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{
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early_printk("please place Xen to be in range of PAGE_SIZE "
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"where PAGE_SIZE is XEN_PT_LEVEL_SIZE( {L3 | L2 | L1} ) "
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"depending on expected SATP_MODE \n"
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"XEN_PT_LEVEL_SIZE is defined in <asm/page.h>\n");
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die();
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}
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index = pt_index(page_table_level, aligned_load_start);
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stage1_pgtbl_root[index] = paddr_to_pte(aligned_load_start,
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PTE_LEAF_DEFAULT | PTE_EXECUTABLE);
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sfence_vma();
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csr_write(CSR_SATP,
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PFN_DOWN((unsigned long)stage1_pgtbl_root) |
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RV_STAGE1_MODE << SATP_MODE_SHIFT);
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if ( (csr_read(CSR_SATP) >> SATP_MODE_SHIFT) == RV_STAGE1_MODE )
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is_mode_supported = true;
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csr_write(CSR_SATP, 0);
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sfence_vma();
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/* Clean MMU root page table */
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stage1_pgtbl_root[index] = paddr_to_pte(0x0, 0x0);
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return is_mode_supported;
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}
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/*
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* setup_initial_pagetables:
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*
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* Build the page tables for Xen that map the following:
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* 1. Calculate page table's level numbers.
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* 2. Init mmu description structure.
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* 3. Check that linker addresses range doesn't overlap
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* with load addresses range
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* 4. Map all linker addresses and load addresses ( it shouldn't
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* be 1:1 mapped and will be 1:1 mapped only in case if
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* linker address is equal to load address ) with
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* RW permissions by default.
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* 5. Setup proper PTE permissions for each section.
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*/
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void __init setup_initial_pagetables(void)
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{
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struct mmu_desc mmu_desc = { CONFIG_PAGING_LEVELS, 0, NULL, NULL };
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/*
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* Access to _start, _end is always PC-relative thereby when access
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* them we will get load adresses of start and end of Xen.
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* To get linker addresses LOAD_TO_LINK() is required to use.
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*/
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unsigned long load_start = (unsigned long)_start;
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unsigned long load_end = (unsigned long)_end;
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unsigned long linker_start = LOAD_TO_LINK(load_start);
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unsigned long linker_end = LOAD_TO_LINK(load_end);
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if ( (linker_start != load_start) &&
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(linker_start <= load_end) && (load_start <= linker_end) )
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{
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early_printk("(XEN) linker and load address ranges overlap\n");
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die();
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}
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if ( !check_pgtbl_mode_support(&mmu_desc, load_start) )
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{
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early_printk("requested MMU mode isn't supported by CPU\n"
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"Please choose different in <asm/config.h>\n");
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die();
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}
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mmu_desc.pgtbl_base = stage1_pgtbl_root;
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mmu_desc.next_pgtbl = stage1_pgtbl_nonroot;
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setup_initial_mapping(&mmu_desc,
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linker_start,
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linker_end,
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load_start);
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}
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void __init noreturn noinline enable_mmu()
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{
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/*
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* Calculate a linker time address of the mmu_is_enabled
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* label and update CSR_STVEC with it.
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* MMU is configured in a way where linker addresses are mapped
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||||
* on load addresses so in a case when linker addresses are not equal
|
||||
* to load addresses, after MMU is enabled, it will cause
|
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* an exception and jump to linker time addresses.
|
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* Otherwise if load addresses are equal to linker addresses the code
|
||||
* after mmu_is_enabled label will be executed without exception.
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*/
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csr_write(CSR_STVEC, LOAD_TO_LINK((unsigned long)&&mmu_is_enabled));
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/* Ensure page table writes precede loading the SATP */
|
||||
sfence_vma();
|
||||
|
||||
/* Enable the MMU and load the new pagetable for Xen */
|
||||
csr_write(CSR_SATP,
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PFN_DOWN((unsigned long)stage1_pgtbl_root) |
|
||||
RV_STAGE1_MODE << SATP_MODE_SHIFT);
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||||
asm volatile ( ".p2align 2" );
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mmu_is_enabled:
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/*
|
||||
* Stack should be re-inited as:
|
||||
* 1. Right now an address of the stack is relative to load time
|
||||
* addresses what will cause an issue in case of load start address
|
||||
* isn't equal to linker start address.
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||||
* 2. Addresses in stack are all load time relative which can be an
|
||||
* issue in case when load start address isn't equal to linker
|
||||
* start address.
|
||||
*
|
||||
* We can't return to the caller because the stack was reseted
|
||||
* and it may have stash some variable on the stack.
|
||||
* Jump to a brand new function as the stack was reseted
|
||||
*/
|
||||
|
||||
switch_stack_and_jump((unsigned long)cpu0_boot_stack + STACK_SIZE,
|
||||
cont_after_mmu_is_enabled);
|
||||
}
|
||||
@@ -2,6 +2,7 @@
|
||||
#include <xen/init.h>
|
||||
|
||||
#include <asm/early_printk.h>
|
||||
#include <asm/mm.h>
|
||||
|
||||
/* Xen stack for bringing up the first CPU. */
|
||||
unsigned char __initdata cpu0_boot_stack[STACK_SIZE]
|
||||
@@ -26,3 +27,13 @@ void __init noreturn start_xen(unsigned long bootcpu_id,
|
||||
|
||||
unreachable();
|
||||
}
|
||||
|
||||
void __init noreturn cont_after_mmu_is_enabled(void)
|
||||
{
|
||||
early_printk("All set up\n");
|
||||
|
||||
for ( ;; )
|
||||
asm volatile ("wfi");
|
||||
|
||||
unreachable();
|
||||
}
|
||||
@@ -172,3 +172,5 @@ ASSERT(IS_ALIGNED(__bss_end, POINTER_ALIGN), "__bss_end is misaligned")
|
||||
|
||||
ASSERT(!SIZEOF(.got), ".got non-empty")
|
||||
ASSERT(!SIZEOF(.got.plt), ".got.plt non-empty")
|
||||
|
||||
ASSERT(_end - _start <= MB(2), "Xen too large for early-boot assumptions")
|
||||