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IOMMU/PCI: consolidate pdev_type() and cache its result for a given device
Add an "unknown" device types as well as one for PCI-to-PCIe bridges (the latter of which other IOMMU code with or without this patch doesn't appear to handle properly). Make sure we don't mistake a device for which we can't access its config space as a legacy PCI device (after all we in fact don't know how to deal with such a device, and hence shouldn't try to). Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: "Zhang, Xiantao" <xiantao.zhang@intel.com>
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b9fba12863
commit
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5 files changed
+40
-27
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@@ -142,7 +142,7 @@ static struct pci_dev *alloc_pdev(struct pci_seg *pseg, u8 bus, u8 devfn)
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spin_lock_init(&pdev->msix_table_lock);
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spin_lock_init(&pdev->msix_table_lock);
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/* update bus2bridge */
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/* update bus2bridge */
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switch ( pdev_type(pseg->nr, bus, devfn) )
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switch ( pdev->type = pdev_type(pseg->nr, bus, devfn) )
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{
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{
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u8 sec_bus, sub_bus;
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u8 sec_bus, sub_bus;
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@@ -182,7 +182,7 @@ static struct pci_dev *alloc_pdev(struct pci_seg *pseg, u8 bus, u8 devfn)
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static void free_pdev(struct pci_seg *pseg, struct pci_dev *pdev)
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static void free_pdev(struct pci_seg *pseg, struct pci_dev *pdev)
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{
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{
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/* update bus2bridge */
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/* update bus2bridge */
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switch ( pdev_type(pseg->nr, pdev->bus, pdev->devfn) )
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switch ( pdev->type )
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{
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{
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u8 dev, func, sec_bus, sub_bus;
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u8 dev, func, sec_bus, sub_bus;
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@@ -200,6 +200,9 @@ static void free_pdev(struct pci_seg *pseg, struct pci_dev *pdev)
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pseg->bus2bridge[sec_bus] = pseg->bus2bridge[pdev->bus];
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pseg->bus2bridge[sec_bus] = pseg->bus2bridge[pdev->bus];
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spin_unlock(&pseg->bus2bridge_lock);
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spin_unlock(&pseg->bus2bridge_lock);
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break;
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break;
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default:
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break;
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}
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}
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list_del(&pdev->alldevs_list);
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list_del(&pdev->alldevs_list);
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@@ -587,20 +590,30 @@ void pci_release_devices(struct domain *d)
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#define PCI_CLASS_BRIDGE_PCI 0x0604
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#define PCI_CLASS_BRIDGE_PCI 0x0604
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int pdev_type(u16 seg, u8 bus, u8 devfn)
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enum pdev_type pdev_type(u16 seg, u8 bus, u8 devfn)
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{
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{
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u16 class_device, creg;
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u16 class_device, creg;
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u8 d = PCI_SLOT(devfn), f = PCI_FUNC(devfn);
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u8 d = PCI_SLOT(devfn), f = PCI_FUNC(devfn);
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int pos = pci_find_cap_offset(seg, bus, d, f, PCI_CAP_ID_EXP);
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int pos = pci_find_cap_offset(seg, bus, d, f, PCI_CAP_ID_EXP);
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class_device = pci_conf_read16(seg, bus, d, f, PCI_CLASS_DEVICE);
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class_device = pci_conf_read16(seg, bus, d, f, PCI_CLASS_DEVICE);
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if ( class_device == PCI_CLASS_BRIDGE_PCI )
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switch ( class_device )
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{
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{
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case PCI_CLASS_BRIDGE_PCI:
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if ( !pos )
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if ( !pos )
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return DEV_TYPE_LEGACY_PCI_BRIDGE;
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return DEV_TYPE_LEGACY_PCI_BRIDGE;
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creg = pci_conf_read16(seg, bus, d, f, pos + PCI_EXP_FLAGS);
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creg = pci_conf_read16(seg, bus, d, f, pos + PCI_EXP_FLAGS);
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return ((creg & PCI_EXP_FLAGS_TYPE) >> 4) == PCI_EXP_TYPE_PCI_BRIDGE ?
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switch ( (creg & PCI_EXP_FLAGS_TYPE) >> 4 )
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DEV_TYPE_PCIe2PCI_BRIDGE : DEV_TYPE_PCIe_BRIDGE;
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{
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case PCI_EXP_TYPE_PCI_BRIDGE:
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return DEV_TYPE_PCIe2PCI_BRIDGE;
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case PCI_EXP_TYPE_PCIE_BRIDGE:
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return DEV_TYPE_PCI2PCIe_BRIDGE;
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}
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return DEV_TYPE_PCIe_BRIDGE;
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case 0x0000: case 0xffff:
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return DEV_TYPE_PCI_UNKNOWN;
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}
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}
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return pos ? DEV_TYPE_PCIe_ENDPOINT : DEV_TYPE_PCI;
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return pos ? DEV_TYPE_PCIe_ENDPOINT : DEV_TYPE_PCI;
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@@ -430,7 +430,6 @@ void io_apic_write_remap_rte(
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static void set_msi_source_id(struct pci_dev *pdev, struct iremap_entry *ire)
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static void set_msi_source_id(struct pci_dev *pdev, struct iremap_entry *ire)
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{
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{
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int type;
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u16 seg;
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u16 seg;
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u8 bus, devfn, secbus;
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u8 bus, devfn, secbus;
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int ret;
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int ret;
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@@ -441,8 +440,7 @@ static void set_msi_source_id(struct pci_dev *pdev, struct iremap_entry *ire)
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seg = pdev->seg;
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seg = pdev->seg;
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bus = pdev->bus;
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bus = pdev->bus;
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devfn = pdev->devfn;
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devfn = pdev->devfn;
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type = pdev_type(seg, bus, devfn);
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switch ( pdev->type )
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switch ( type )
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{
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{
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case DEV_TYPE_PCIe_BRIDGE:
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case DEV_TYPE_PCIe_BRIDGE:
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case DEV_TYPE_PCIe2PCI_BRIDGE:
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case DEV_TYPE_PCIe2PCI_BRIDGE:
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@@ -474,7 +472,7 @@ static void set_msi_source_id(struct pci_dev *pdev, struct iremap_entry *ire)
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default:
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default:
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dprintk(XENLOG_WARNING VTDPREFIX,
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dprintk(XENLOG_WARNING VTDPREFIX,
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"d%d: unknown(%u): %04x:%02x:%02x.%u\n",
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"d%d: unknown(%u): %04x:%02x:%02x.%u\n",
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pdev->domain->domain_id, type,
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pdev->domain->domain_id, pdev->type,
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seg, bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
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seg, bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
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break;
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break;
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}
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}
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@@ -1419,7 +1419,6 @@ static int domain_context_mapping(
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{
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{
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struct acpi_drhd_unit *drhd;
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struct acpi_drhd_unit *drhd;
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int ret = 0;
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int ret = 0;
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u32 type;
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u8 seg = pdev->seg, bus = pdev->bus, secbus;
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u8 seg = pdev->seg, bus = pdev->bus, secbus;
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drhd = acpi_find_matched_drhd_unit(pdev);
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drhd = acpi_find_matched_drhd_unit(pdev);
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@@ -1428,8 +1427,7 @@ static int domain_context_mapping(
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ASSERT(spin_is_locked(&pcidevs_lock));
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ASSERT(spin_is_locked(&pcidevs_lock));
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type = pdev_type(seg, bus, devfn);
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switch ( pdev->type )
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switch ( type )
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{
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{
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case DEV_TYPE_PCIe_BRIDGE:
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case DEV_TYPE_PCIe_BRIDGE:
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case DEV_TYPE_PCIe2PCI_BRIDGE:
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case DEV_TYPE_PCIe2PCI_BRIDGE:
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@@ -1479,7 +1477,7 @@ static int domain_context_mapping(
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default:
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default:
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dprintk(XENLOG_ERR VTDPREFIX, "d%d:unknown(%u): %04x:%02x:%02x.%u\n",
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dprintk(XENLOG_ERR VTDPREFIX, "d%d:unknown(%u): %04x:%02x:%02x.%u\n",
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domain->domain_id, type,
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domain->domain_id, pdev->type,
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seg, bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
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seg, bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
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ret = -EINVAL;
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ret = -EINVAL;
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break;
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break;
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@@ -1551,7 +1549,6 @@ static int domain_context_unmap(
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struct acpi_drhd_unit *drhd;
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struct acpi_drhd_unit *drhd;
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struct iommu *iommu;
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struct iommu *iommu;
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int ret = 0;
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int ret = 0;
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u32 type;
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u8 seg = pdev->seg, bus = pdev->bus, tmp_bus, tmp_devfn, secbus;
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u8 seg = pdev->seg, bus = pdev->bus, tmp_bus, tmp_devfn, secbus;
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int found = 0;
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int found = 0;
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@@ -1560,8 +1557,7 @@ static int domain_context_unmap(
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return -ENODEV;
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return -ENODEV;
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iommu = drhd->iommu;
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iommu = drhd->iommu;
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type = pdev_type(seg, bus, devfn);
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switch ( pdev->type )
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switch ( type )
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{
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{
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case DEV_TYPE_PCIe_BRIDGE:
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case DEV_TYPE_PCIe_BRIDGE:
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case DEV_TYPE_PCIe2PCI_BRIDGE:
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case DEV_TYPE_PCIe2PCI_BRIDGE:
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@@ -1608,7 +1604,7 @@ static int domain_context_unmap(
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default:
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default:
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dprintk(XENLOG_ERR VTDPREFIX, "d%d:unknown(%u): %04x:%02x:%02x.%u\n",
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dprintk(XENLOG_ERR VTDPREFIX, "d%d:unknown(%u): %04x:%02x:%02x.%u\n",
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domain->domain_id, type,
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domain->domain_id, pdev->type,
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seg, bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
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seg, bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
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ret = -EINVAL;
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ret = -EINVAL;
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goto out;
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goto out;
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+12
-9
@@ -62,6 +62,17 @@ struct pci_dev {
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const u16 seg;
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const u16 seg;
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const u8 bus;
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const u8 bus;
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const u8 devfn;
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const u8 devfn;
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enum pdev_type {
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DEV_TYPE_PCI_UNKNOWN,
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DEV_TYPE_PCIe_ENDPOINT,
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DEV_TYPE_PCIe_BRIDGE, // PCIe root port, switch
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DEV_TYPE_PCIe2PCI_BRIDGE, // PCIe-to-PCI/PCIx bridge
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DEV_TYPE_PCI2PCIe_BRIDGE, // PCI/PCIx-to-PCIe bridge
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DEV_TYPE_LEGACY_PCI_BRIDGE, // Legacy PCI bridge
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DEV_TYPE_PCI,
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} type;
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struct pci_dev_info info;
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struct pci_dev_info info;
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struct arch_pci_dev arch;
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struct arch_pci_dev arch;
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struct {
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struct {
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@@ -83,18 +94,10 @@ struct pci_dev {
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extern spinlock_t pcidevs_lock;
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extern spinlock_t pcidevs_lock;
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enum {
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DEV_TYPE_PCIe_ENDPOINT,
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DEV_TYPE_PCIe_BRIDGE, // PCIe root port, switch
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DEV_TYPE_PCIe2PCI_BRIDGE, // PCIe-to-PCI/PCIx bridge
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DEV_TYPE_LEGACY_PCI_BRIDGE, // Legacy PCI bridge
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DEV_TYPE_PCI,
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};
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bool_t pci_known_segment(u16 seg);
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bool_t pci_known_segment(u16 seg);
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int pci_device_detect(u16 seg, u8 bus, u8 dev, u8 func);
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int pci_device_detect(u16 seg, u8 bus, u8 dev, u8 func);
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int scan_pci_devices(void);
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int scan_pci_devices(void);
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int pdev_type(u16 seg, u8 bus, u8 devfn);
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enum pdev_type pdev_type(u16 seg, u8 bus, u8 devfn);
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int find_upstream_bridge(u16 seg, u8 *bus, u8 *devfn, u8 *secbus);
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int find_upstream_bridge(u16 seg, u8 *bus, u8 *devfn, u8 *secbus);
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struct pci_dev *pci_lock_pdev(int seg, int bus, int devfn);
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struct pci_dev *pci_lock_pdev(int seg, int bus, int devfn);
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struct pci_dev *pci_lock_domain_pdev(
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struct pci_dev *pci_lock_domain_pdev(
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@@ -371,6 +371,9 @@
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#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
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#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
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#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
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#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
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#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
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#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
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#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIE Bridge */
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#define PCI_EXP_TYPE_RC_END 0x9 /* Root Complex Integrated Endpoint */
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#define PCI_EXP_TYPE_RC_EC 0xa /* Root Complex Event Collector */
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#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
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#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
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#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
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#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
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#define PCI_EXP_DEVCAP 4 /* Device capabilities */
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#define PCI_EXP_DEVCAP 4 /* Device capabilities */
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