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x86emul: support AVX512F legacy-equivalent packed int/FP conversion insns
... including the two AVX512DQ forms which shared encodings, just with EVEX.W set there. VCVTDQ2PD, sharing its main opcode with others, needs a "manual" override of disp8scale. The simd_size changes for the twobyte_table[] entries are benign to pre-existing code, but allow decode_disp8scale() to work as is here. The at this point wrong placement of the 0xe6 case block is once again in anticipation of further additions of case labels. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
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Jan Beulich committed
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@@ -109,8 +109,12 @@ static const struct test avx512f_all[] = {
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INSN_FP(cmp, 0f, c2),
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INSN(comisd, 66, 0f, 2f, el, q, el),
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INSN(comiss, , 0f, 2f, el, d, el),
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INSN(cvtdq2pd, f3, 0f, e6, vl_2, d, vl),
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INSN(cvtdq2ps, , 0f, 5b, vl, d, vl),
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INSN(cvtpd2dq, f2, 0f, e6, vl, q, vl),
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INSN(cvtpd2ps, 66, 0f, 5a, vl, q, vl),
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INSN(cvtph2ps, 66, 0f38, 13, vl_2, d_nb, vl),
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INSN(cvtps2dq, 66, 0f, 5b, vl, d, vl),
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INSN(cvtps2pd, , 0f, 5a, vl_2, d, vl),
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INSN(cvtps2ph, 66, 0f3a, 1d, vl_2, d_nb, vl),
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INSN(cvtsd2ss, f2, 0f, 5a, el, q, el),
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@@ -398,6 +402,8 @@ static const struct test avx512dq_all[] = {
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INSN_PFP(and, 0f, 54),
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INSN_PFP(andn, 0f, 55),
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INSN(broadcasti32x2, 66, 0f38, 59, el_2, d, vl),
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INSN(cvtqq2pd, f3, 0f, e6, vl, q, vl),
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INSN(cvtqq2ps, , 0f, 5b, vl, q, vl),
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INSN_PFP(or, 0f, 56),
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// pmovd2m, f3, 0f38, 39, d
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// pmovm2, f3, 0f38, 38, dq
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@@ -92,6 +92,13 @@ static inline bool _to_bool(byte_vec_t bv)
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# define to_int(x) ((vec_t){ (int)(x)[0] })
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#elif VEC_SIZE == 8 && FLOAT_SIZE == 4 && defined(__3dNOW__)
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# define to_int(x) __builtin_ia32_pi2fd(__builtin_ia32_pf2id(x))
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#elif defined(FLOAT_SIZE) && VEC_SIZE > FLOAT_SIZE && defined(__AVX512F__) && \
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(VEC_SIZE == 64 || defined(__AVX512VL__))
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# if FLOAT_SIZE == 4
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# define to_int(x) BR(cvtdq2ps, _mask, BR(cvtps2dq, _mask, x, (vsi_t)undef(), ~0), undef(), ~0)
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# elif FLOAT_SIZE == 8
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# define to_int(x) B(cvtdq2pd, _mask, BR(cvtpd2dq, _mask, x, (vsi_half_t){}, ~0), undef(), ~0)
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# endif
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#elif VEC_SIZE == 16 && defined(__SSE2__)
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# if FLOAT_SIZE == 4
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# define to_int(x) __builtin_ia32_cvtdq2ps(__builtin_ia32_cvtps2dq(x))
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@@ -1142,15 +1149,21 @@ int simd_test(void)
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touch(src);
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if ( !eq(x * -alt, -src) ) return __LINE__;
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# if defined(recip) && defined(to_int)
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# ifdef to_int
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touch(src);
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x = to_int(src);
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touch(src);
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if ( !eq(x, src) ) return __LINE__;
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# ifdef recip
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touch(src);
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x = recip(src);
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touch(src);
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touch(x);
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if ( !eq(to_int(recip(x)), src) ) return __LINE__;
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# ifdef rsqrt
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# ifdef rsqrt
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x = src * src;
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touch(x);
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y = rsqrt(x);
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@@ -1158,6 +1171,7 @@ int simd_test(void)
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if ( !eq(to_int(recip(y)), src) ) return __LINE__;
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touch(src);
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if ( !eq(to_int(y), to_int(recip(src))) ) return __LINE__;
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# endif
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# endif
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# endif
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@@ -244,6 +244,7 @@ asm ( ".macro override insn \n\t"
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OVR_INT(broadcast);
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OVR_SFP(broadcast);
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OVR_SFP(comi);
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OVR_VFP(cvtdq2);
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OVR_FP(add);
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OVR_INT(add);
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OVR_BW(adds);
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@@ -330,13 +331,19 @@ REN(pandn, , d);
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REN(por, , d);
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REN(pxor, , d);
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# endif
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OVR(cvtpd2dqx);
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OVR(cvtpd2dqy);
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OVR(cvtpd2psx);
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OVR(cvtpd2psy);
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OVR(cvtph2ps);
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OVR(cvtps2dq);
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OVR(cvtps2pd);
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OVR(cvtps2ph);
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OVR(cvtsd2ss);
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OVR(cvtss2sd);
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OVR(cvttpd2dqx);
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OVR(cvttpd2dqy);
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OVR(cvttps2dq);
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OVR(movddup);
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OVR(movntdq);
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OVR(movntdqa);
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@@ -311,7 +311,7 @@ static const struct twobyte_table {
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[0x54 ... 0x57] = { DstImplicit|SrcMem|ModRM, simd_packed_fp, d8s_vl },
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[0x58 ... 0x59] = { DstImplicit|SrcMem|ModRM, simd_any_fp, d8s_vl },
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[0x5a] = { DstImplicit|SrcMem|ModRM|Mov, simd_any_fp, d8s_vl },
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[0x5b] = { DstImplicit|SrcMem|ModRM|Mov, simd_other },
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[0x5b] = { DstImplicit|SrcMem|ModRM|Mov, simd_packed_fp, d8s_vl },
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[0x5c ... 0x5f] = { DstImplicit|SrcMem|ModRM, simd_any_fp, d8s_vl },
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[0x60 ... 0x62] = { DstImplicit|SrcMem|ModRM, simd_other, d8s_vl },
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[0x63 ... 0x67] = { DstImplicit|SrcMem|ModRM, simd_packed_int, d8s_vl },
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@@ -375,7 +375,7 @@ static const struct twobyte_table {
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[0xe0] = { DstImplicit|SrcMem|ModRM, simd_packed_int, d8s_vl },
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[0xe1 ... 0xe2] = { DstImplicit|SrcMem|ModRM, simd_128, 4 },
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[0xe3 ... 0xe5] = { DstImplicit|SrcMem|ModRM, simd_packed_int, d8s_vl },
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[0xe6] = { DstImplicit|SrcMem|ModRM|Mov, simd_other },
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[0xe6] = { DstImplicit|SrcMem|ModRM|Mov, simd_packed_fp, d8s_vl },
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[0xe7] = { DstMem|SrcImplicit|ModRM|Mov, simd_packed_int, d8s_vl },
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[0xe8 ... 0xef] = { DstImplicit|SrcMem|ModRM, simd_packed_int, d8s_vl },
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[0xf0] = { DstImplicit|SrcMem|ModRM|Mov, simd_other },
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@@ -3049,6 +3049,11 @@ x86_decode(
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if ( disp8scale == 2 && evex.pfx == vex_f3 )
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disp8scale = 3;
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break;
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case 0xe6: /* vcvtdq2pd needs special casing */
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if ( disp8scale && evex.pfx == vex_f3 && !evex.w && !evex.brs )
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--disp8scale;
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break;
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}
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break;
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@@ -6561,6 +6566,22 @@ x86_emulate(
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op_bytes = 16 << vex.l;
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goto simd_0f_cvt;
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case X86EMUL_OPC_EVEX_66(0x0f, 0x5b): /* vcvtps2dq [xyz]mm/mem,[xyz]mm{k} */
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case X86EMUL_OPC_EVEX_F3(0x0f, 0x5b): /* vcvttps2dq [xyz]mm/mem,[xyz]mm{k} */
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generate_exception_if(evex.w, EXC_UD);
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/* fall through */
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case X86EMUL_OPC_EVEX(0x0f, 0x5b): /* vcvtdq2ps [xyz]mm/mem,[xyz]mm{k} */
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/* vcvtqq2ps [xyz]mm/mem,{x,y}mm{k} */
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if ( evex.w )
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host_and_vcpu_must_have(avx512dq);
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else
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host_and_vcpu_must_have(avx512f);
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if ( ea.type != OP_REG || !evex.brs )
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avx512_vlen_check(false);
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d |= TwoOp;
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op_bytes = 16 << evex.lr;
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goto simd_zmm;
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CASE_SIMD_PACKED_INT(0x0f, 0x60): /* punpcklbw {,x}mm/mem,{,x}mm */
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case X86EMUL_OPC_VEX_66(0x0f, 0x60): /* vpunpcklbw {x,y}mm/mem,{x,y}mm,{x,y}mm */
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CASE_SIMD_PACKED_INT(0x0f, 0x61): /* punpcklwd {,x}mm/mem,{,x}mm */
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@@ -7227,6 +7248,27 @@ x86_emulate(
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op_bytes = 8;
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goto simd_0f_xmm;
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case X86EMUL_OPC_EVEX_66(0x0f, 0xe6): /* vcvttpd2dq [xyz]mm/mem,{x,y}mm{k} */
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case X86EMUL_OPC_EVEX_F2(0x0f, 0xe6): /* vcvtpd2dq [xyz]mm/mem,{x,y}mm{k} */
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generate_exception_if(!evex.w, EXC_UD);
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/* fall through */
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case X86EMUL_OPC_EVEX_F3(0x0f, 0xe6): /* vcvtdq2pd {x,y}mm/mem,[xyz]mm{k} */
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/* vcvtqq2pd [xyz]mm/mem,[xyz]mm{k} */
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if ( evex.pfx != vex_f3 )
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host_and_vcpu_must_have(avx512f);
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else if ( evex.w )
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host_and_vcpu_must_have(avx512dq);
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else
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{
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host_and_vcpu_must_have(avx512f);
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generate_exception_if(ea.type != OP_MEM && evex.brs, EXC_UD);
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}
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if ( ea.type != OP_REG || !evex.brs )
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avx512_vlen_check(false);
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d |= TwoOp;
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op_bytes = 8 << (evex.w + evex.lr);
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goto simd_zmm;
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case X86EMUL_OPC_F2(0x0f, 0xf0): /* lddqu m128,xmm */
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case X86EMUL_OPC_VEX_F2(0x0f, 0xf0): /* vlddqu mem,{x,y}mm */
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generate_exception_if(ea.type != OP_MEM, EXC_UD);
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