From f49bbd301b0e9eb81cff2dddf6862ec469cf8ef9 Mon Sep 17 00:00:00 2001 From: Andrew Cooper Date: Mon, 1 Dec 2025 21:56:50 +0000 Subject: [PATCH] x86/amd: Fold another DE_CFG edit into amd_init_de_cfg() As amd_init_de_cfg() states, it's only safe for there to be one location writing to DE_CFG. This happens to be a latent bug rather than a real one because Fam12h CPUs aren't SMT-capable. Nevertheless, group it together with the other DE_CFG modifications. This removes a printk() which is not noteworthy, and skips the adjustment entirely under virt, where the attempted write wouldn't have stuck anyway. Fixes: d0c75dc4c028 ("x86/amd: Fix race editing DE_CFG") Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- xen/arch/x86/cpu/amd.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index 8c5bdf0bd5..f9bcf4ed2c 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -920,6 +920,13 @@ void amd_init_de_cfg(const struct cpuinfo_x86 *c) if ( zenbleed_use_chickenbit() ) new |= (1 << 9); + /* + * Erratum #665, doc 44739. Integer divide instructions may cause + * unpredictable behaviour. + */ + if ( c->family == 0x12 ) + new |= 1U << 31; + /* Avoid reading DE_CFG if we don't intend to change anything. */ if ( !new ) return; @@ -1201,15 +1208,6 @@ static void cf_check init_amd(struct cpuinfo_x86 *c) smp_processor_id()); wrmsrl(MSR_AMD64_LS_CFG, value | (1 << 15)); } - } else if (c->x86 == 0x12) { - rdmsrl(MSR_AMD64_DE_CFG, value); - if (!(value & (1U << 31))) { - if (c == &boot_cpu_data || opt_cpu_info) - printk_once(XENLOG_WARNING - "CPU%u: Applying workaround for erratum 665\n", - smp_processor_id()); - wrmsrl(MSR_AMD64_DE_CFG, value | (1U << 31)); - } } /* AMD CPUs do not support SYSENTER outside of legacy mode. */