diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c
index 56b22a2ff3..b2bca4dcf8 100644
--- a/xen/arch/x86/acpi/cpu_idle.c
+++ b/xen/arch/x86/acpi/cpu_idle.c
@@ -1065,6 +1065,24 @@ static void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flag
      */
     if ( c->vendor == X86_VENDOR_INTEL )
         flags->bm_control = 0;
+
+    if ( (c->vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) &&
+         c->family >= 0x17 )
+    {
+        /*
+         * For all AMD Zen or newer CPUs that support C3, caches
+         * should not be flushed by software while entering C3
+         * type state. Set bm_check to 1 so that Xen doesn't
+         * need to execute cache flush operation.
+         */
+        flags->bm_check = 1;
+        /*
+         * In current AMD C state implementation ARB_DIS is no longer
+         * used. So set bm_control to zero to indicate ARB_DIS is not
+         * required while entering C3 type state.
+         */
+        flags->bm_control = 0;
+    }
 }
 
 #define VENDOR_INTEL                   (1)